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ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: C:\Documents and Settings\Owner\桌面\《单片机C语言程序设计实训100例——基于8051+Proteus仿真》案例压缩包\第 01 篇 基础部分\01 闪烁的LED\闪烁的LED.DSN Doc.

// Verilog model created from schematic andnor2.sch - Wed Nov 13 17:04:16 2002 `timescale 1ns / 1ps module andnor2(in1, in2, in3, in4, out_t); input in1; input in2; input in3; input

// Verilog model created from schematic andnor2.sch - Wed Nov 13 17:04:16 2002 `timescale 1ns / 1ps module andnor2(in1, in2, in3, in4, out_t); input in1; input in2; input in3; input

SCHEMATIC START ; // created by map version G.28 on Sun Feb 26 18:30:38 2006 COMP "sda_pin" LOCATE = SITE "P35" LEVEL 1; COMP "i2c_rdata" LOCATE = SITE "P14" LEVEL 1; COMP "i2c_rdata" L

SCHEMATIC START ; // created by map version G.28 on Sun Feb 26 18:30:38 2006 COMP "sda_pin" LOCATE = SITE "P35" LEVEL 1; COMP "i2c_rdata" LOCATE = SITE "P14" LEVEL 1; COMP "i2c_rdata" L

JDF B // Created by Version 7.0 PROJECT DDR2_eval.syn DESIGN ddr2_eval Normal DEVKIT LFE2M35E-6F256CES ENTRY Schematic/Verilog HDL MODULE ..\..\models\ecp2m\pll_120M.v MODSTYLE pll_120M Normal

SCHEMATIC START ; // created by map version E.38 on Sat Aug 24 23:10:39 2002 COMP "CSC_module/cr_g_kcm(11)" LOCATE = SITE "CLB_R7C14.S0" LEVEL 1; COMP "CSC_module/y_g_kcm(13)" LOCATE = SITE "CLB_

SCHEMATIC START ; // created by map version E.38 on Sat Aug 24 23:10:39 2002 COMP "CSC_module/cr_g_kcm(11)" LOCATE = SITE "CLB_R7C14.S0" LEVEL 1; COMP "CSC_module/y_g_kcm(13)" LOCATE = SITE "CLB_

SCHEMATIC START ; // created by map version E.38 on Wed Dec 15 14:45:34 2004 COMP "K5" LOCATE = SITE "P208" LEVEL 1; COMP "K5" LOCATE = SITE "P207" LEVEL 1; COMP "K5" LOCATE = SITE "P2

STYFILENAME=mico8.sty PROJECT=mico8 ENTRY=Schematic/VHDL WORKING_PATH=c:/projects/refdesigns/mico8/mico8_demonstration_design_v3/block_mico8_ecp2_6 MODULE=mico8 TOP_FILE=mico8.sch EDF_FILE_LIST=