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example_en_16bit_s.v
/* Verilog Model Created from SCS Schematic example_en_16bit_s.sch
Aug 14, 2003 12:15 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
example_en_8bit_s.v
/* Verilog Model Created from SCS Schematic example_en_8bit_s.sch
Aug 14, 2003 11:35 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOGI
example_en_8bit_s.vhd
-- VHDL Model Created from SCS Schematic example_en_8bit_s.sch
-- Aug 14, 2003 11:35
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.al
example_en_24bit_s.v
/* Verilog Model Created from SCS Schematic example_en_24bit_s.sch
Aug 14, 2003 16:14 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
sim1.out.1
**** 12/31/05 17:33:28 ******* PSpice 10.1.0 (Jan 2003) ******* ID# 1111111111
** Profile: "SCHEMATIC1-sim1" [ C:\_E_Research\pemfc500\ModelPosted\PspiceModel\Version 10.1.0.p001\etmodel-pspicef
sim1.out
**** 01/01/06 12:50:00 ******* PSpice 10.1.0 (Jan 2003) ******* ID# 1111111111
** Profile: "SCHEMATIC1-sim1" [ C:\_E_Research\pemfc500\ModelPosted\PspiceModel\Version 10.1.0.p001\etmodel-pspice
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\awork\lx\proteus\DA\DAC0808\DAC0808ls373电压PP2.7\DAC0808ls373.DSN
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lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\awork\lx\proteus\DA\DAC0808\DAC0808ls373电压P3.5\DAC0808ls373.DSN
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lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\awork\lx\proteus\DA\DAC0808\DAC0808ls373锯齿波\DAC0808ls373锯齿波.DSN
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lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\a-51新书\book\ex8\ex8-3\ex8-3.DSN
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Created: 13/12/06
Mo