📄 example_en_8bit_s.vhd
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-- VHDL Model Created from SCS Schematic example_en_8bit_s.sch
-- Aug 14, 2003 11:35
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_EN_4BIT_S is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
qa_r : Out STD_LOGIC;
qb_r : Out STD_LOGIC;
qc_r : Out STD_LOGIC;
qd_r : Out STD_LOGIC );
end COUNTER_EN_4BIT_S;
architecture SCHEMATIC of COUNTER_EN_4BIT_S is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal BCD_a : STD_LOGIC;
signal ABCDE_a : STD_LOGIC;
signal ED_a : STD_LOGIC;
constant GND : STD_LOGIC := '0';
constant VCC : STD_LOGIC := '1';
signal qa_r_DUMMY : STD_LOGIC;
signal qb_r_DUMMY : STD_LOGIC;
signal qc_r_DUMMY : STD_LOGIC;
signal qd_r_DUMMY : STD_LOGIC;
component SUPER_LOGIC
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
\NS\ : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
PP : In STD_LOGIC;
PS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
Q2Z : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
begin
qa_r <= qa_r_DUMMY;
qb_r <= qb_r_DUMMY;
qc_r <= qc_r_DUMMY;
qd_r <= qd_r_DUMMY;
I1 : SUPER_LOGIC
Port Map ( A1=>BCD_a, A2=>GND, A3=>ED_a, A4=>GND, A5=>qa_r_DUMMY,
A6=>GND, B1=>ED_a, B2=>qc_r_DUMMY, C1=>qc_r_DUMMY,
C2=>ED_a, D1=>qb_r_DUMMY, D2=>GND, E1=>VCC,
E2=>qb_r_DUMMY, F1=>qc_r_DUMMY, F2=>GND, F3=>qd_r_DUMMY,
F4=>GND, F5=>VCC, F6=>GND, MP=>GND, MS=>qc_r_DUMMY,
NP=>enable, \NS\=>GND, OP=>GND, OS=>GND, PP=>GND,
PS=>GND, QC=>clk, QR=>clear, QS=>GND, AZ=>ABCDE_a,
FZ=>open, NZ=>open, OZ=>open, Q2Z=>qb_r_DUMMY,
QZ=>qc_r_DUMMY );
I2 : SUPER_LOGIC
Port Map ( A1=>enable, A2=>GND, A3=>qd_r_DUMMY, A4=>GND, A5=>VCC,
A6=>GND, B1=>qa_r_DUMMY, B2=>GND, C1=>VCC,
C2=>qa_r_DUMMY, D1=>enable, D2=>qd_r_DUMMY,
E1=>qd_r_DUMMY, E2=>enable, F1=>qb_r_DUMMY, F2=>GND,
F3=>qc_r_DUMMY, F4=>GND, F5=>qd_r_DUMMY, F6=>GND,
MP=>enable, MS=>GND, NP=>GND, \NS\=>qd_r_DUMMY, OP=>GND,
OS=>GND, PP=>GND, PS=>GND, QC=>clk, QR=>clear, QS=>GND,
AZ=>ED_a, FZ=>BCD_a, NZ=>open, OZ=>open,
Q2Z=>qd_r_DUMMY, QZ=>qa_r_DUMMY );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_EN_8BIT_S is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
f_enable_1 : Out STD_LOGIC;
f_enable_2 : Out STD_LOGIC );
end COUNTER_EN_8BIT_S;
architecture SCHEMATIC of COUNTER_EN_8BIT_S is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal enable_1_a : STD_LOGIC;
signal fo_enable_r : STD_LOGIC;
signal enable_buf_a : STD_LOGIC;
signal enable_2_r : STD_LOGIC;
constant VCC : STD_LOGIC := '1';
constant GND : STD_LOGIC := '0';
signal count_DUMMY : STD_LOGIC_VECTOR (7 downto 0);
signal f_enable_1_DUMMY : STD_LOGIC;
signal f_enable_2_DUMMY : STD_LOGIC;
component COUNTER_EN_4BIT_S
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
qa_r : Out STD_LOGIC;
qb_r : Out STD_LOGIC;
qc_r : Out STD_LOGIC;
qd_r : Out STD_LOGIC );
end component;
component OUTPAD_25UM
Port ( A : In STD_LOGIC;
P : Out STD_LOGIC );
end component;
component SUPER_LOGIC
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
\NS\ : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
PP : In STD_LOGIC;
PS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
Q2Z : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
begin
count(7 downto 0) <= count_DUMMY(7 downto 0);
f_enable_1 <= f_enable_1_DUMMY;
f_enable_2 <= f_enable_2_DUMMY;
I20 : COUNTER_EN_4BIT_S
Port Map ( clear=>clear, clk=>clk, enable=>enable_1_a,
qa_r=>count_DUMMY(7), qb_r=>count_DUMMY(6),
qc_r=>count_DUMMY(5), qd_r=>count_DUMMY(4) );
I21 : COUNTER_EN_4BIT_S
Port Map ( clear=>clear, clk=>clk, enable=>enable_buf_a,
qa_r=>count_DUMMY(3), qb_r=>count_DUMMY(2),
qc_r=>count_DUMMY(1), qd_r=>count_DUMMY(0) );
I17 : OUTPAD_25UM
Port Map ( A=>enable_2_r, P=>f_enable_2_DUMMY );
I18 : OUTPAD_25UM
Port Map ( A=>enable_1_a, P=>f_enable_1_DUMMY );
I19 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(7), A2=>gnd, A3=>count_DUMMY(6),
A4=>gnd, A5=>count_DUMMY(5), A6=>gnd, B1=>vcc, B2=>gnd,
C1=>gnd, C2=>gnd, D1=>gnd, D2=>gnd, E1=>gnd, E2=>gnd,
F1=>enable, F2=>gnd, F3=>vcc, F4=>gnd, F5=>vcc, F6=>gnd,
MP=>gnd, MS=>count_DUMMY(4), NP=>gnd, \NS\=>gnd,
OP=>vcc, OS=>gnd, PP=>gnd, PS=>gnd, QC=>clk, QR=>clear,
QS=>gnd, AZ=>open, FZ=>enable_buf_a, NZ=>open, OZ=>open,
Q2Z=>open, QZ=>enable_2_r );
I14 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(3), A2=>gnd, A3=>count_DUMMY(2),
A4=>gnd, A5=>count_DUMMY(1), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>gnd, C2=>gnd, D1=>count_DUMMY(0), D2=>gnd, E1=>vcc,
E2=>count_DUMMY(0), F1=>fo_enable_r, F2=>gnd,
F3=>enable, F4=>gnd, F5=>vcc, F6=>gnd, MP=>gnd, MS=>gnd,
NP=>gnd, \NS\=>enable, OP=>vcc, OS=>gnd, PP=>gnd,
PS=>gnd, QC=>clk, QR=>clear, QS=>gnd, AZ=>open,
FZ=>enable_1_a, NZ=>open, OZ=>open, Q2Z=>open,
QZ=>fo_enable_r );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity example_en_8bit_s is
Port ( clear_in : In STD_LOGIC;
clk_in : In STD_LOGIC;
enable_in : In STD_LOGIC;
count_out : Out STD_LOGIC_VECTOR (7 downto 0) );
end example_en_8bit_s;
architecture SCHEMATIC of example_en_8bit_s is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal count : STD_LOGIC_VECTOR (7 downto 0);
signal count_reg : STD_LOGIC_VECTOR (7 downto 0);
signal enable_reg : STD_LOGIC;
signal enable : STD_LOGIC;
signal clear : STD_LOGIC;
signal clk : STD_LOGIC;
signal count_out_DUMMY : STD_LOGIC_VECTOR (7 downto 0);
component COUNTER_EN_8BIT_S
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
f_enable_1 : Out STD_LOGIC;
f_enable_2 : Out STD_LOGIC );
end component;
component RG8_25UM
Port ( CLK : In STD_LOGIC;
D : In STD_LOGIC_VECTOR (7 downto 0);
Q : Out STD_LOGIC_VECTOR (7 downto 0) );
end component;
component DFF_2
Port ( CLK : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
Q1 : Out STD_LOGIC;
Q2 : Out STD_LOGIC );
end component;
component OPAD8_25UM
Port ( A : In STD_LOGIC_VECTOR (7 downto 0);
P : Out STD_LOGIC_VECTOR (7 downto 0) );
end component;
component INPAD_25UM
Port ( P : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
component CKPAD_25UM
Port ( P : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
begin
count_out(7 downto 0) <= count_out_DUMMY(7 downto 0);
I9 : COUNTER_EN_8BIT_S
Port Map ( clear=>clear, clk=>clk, enable=>enable_reg,
count(7 downto 0)=>count(7 downto 0), f_enable_1=>open,
f_enable_2=>open );
I1 : RG8_25UM
Port Map ( CLK=>clk, D(7 downto 0)=>count(7 downto 0),
Q(7 downto 0)=>count_reg(7 downto 0) );
I2 : DFF_2
Port Map ( CLK=>clk, D1=>enable, D2=>enable, Q1=>enable_reg,
Q2=>open );
I3 : OPAD8_25UM
Port Map ( A(7 downto 0)=>count_reg(7 downto 0),
P(7 downto 0)=>count_out_DUMMY(7 downto 0) );
I4 : INPAD_25UM
Port Map ( P=>enable_in, Q=>enable );
I5 : CKPAD_25UM
Port Map ( P=>clk_in, Q=>clk );
I6 : CKPAD_25UM
Port Map ( P=>clear_in, Q=>clear );
end SCHEMATIC;
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