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example_16bit_load.vhd
-- VHDL Model Created from SCS Schematic example_16bit_load.sch
-- Aug 15, 2003 11:19
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
example_32bit_load.vhd
-- VHDL Model Created from SCS Schematic example_32bit_load.sch
-- Aug 15, 2003 13:22
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
sim1.sim
@OrCAD Simulation Server Version: 1.0
@Settings: 0 1
@General:
ProfileName= "sim1"
ProfileFile= "sim1.sim"
Connectivity= "SCHEMATIC1.net"
NetlistFile= "sim1.cir"
DataFile= "sim1.dat"
Ou
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\awork\lx\proteus\DA\DAC0808\DAC0808ls373电压\DAC0808ls373.DSN
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12-4.pdf
{COMPONENT C:\DOCUMENTS AND SETTINGS\H\桌面\新建文件夹\12-4.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Tue Aug 08 17:22:
矩阵键盘.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: C:\Users\吴敦为\Desktop\暑假工作室\矩阵键盘\矩阵键盘.DSN
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Created: 08/07/17
Mod
schcvt.ini
[General]
Default Input=Protel 99SE/DXP
Default Output=PADS Logic
[Protel 99SE/DXP -> PADS Logic - General]
Config File=C:\Program Files\Mentor Graphics\Translators\Schematic\protel2pl.cnv
[Prote
des0209_11_sch_10.onl
(PCB DES0209_11_SCH_10
(description
(timeStamp "2005 06 02 18 39 35")
(program "CAPTURE.EXE" (Version "10.3.0.p001"))
(source "Original data from OrCAD/CAPTURE schematic")
(title "Des020
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: E:\科目\AVR\AVR单片机编程实例\AVR单片机\44键盘\44键盘\键盘扫描.DSN
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lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\a-51新书\book\ex6\6-4\ex6-4.DSN
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Author:
Created: 06/04/19
Modi