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lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
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Design: E:\Study\proteus\8051单片机\DS1302时钟\DS1302.DSN
Doc. no.:
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Author:
Created: 05
claadd8s.v
/* Verilog Model Created from SCS Schematic claadd8s.sch
Mar 22, 1996 23:48 */
/* Automatically generated by hvveri version 5.1 */
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR
lcd1602.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\Proteus 7.1\Proteus 仿真实例\8051单片机\字符液晶1602\LCD1602.DSN
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claadd8s.v
/* Verilog Model Created from SCS Schematic claadd8s.sch
Mar 22, 1996 23:48 */
/* Automatically generated by hvveri version 5.1 */
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR
bias.out.1
**** 04/23/07 22:20:36 ******* PSpice 10.3.0 (Jan 2004) ******* ID# 1111111111
** Profile: "SCHEMATIC1-bias" [ D:\Christophe\Livres\Spice simus 2\OrCAD book distribution\Chapitre7\flyback-PSpic
bias.out.1
**** 04/23/07 22:20:36 ******* PSpice 10.3.0 (Jan 2004) ******* ID# 1111111111
** Profile: "SCHEMATIC1-bias" [ D:\Christophe\Livres\Spice simus 2\OrCAD book distribution\Chapitre7\flyback-PSpic
stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input
stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\教学文件\单片机资料\LCD_now\12864\lcd_design200.DSN
Doc. no.:
Revision:
Author:
Created: 0
stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input