claadd8s.v

比较先进的直接数字频率合成器的设计。可用于频率的合成。

/* Verilog Model Created from SCS Schematic claadd8s.sch 
   Mar 22, 1996 23:48 */

/* Automatically generated by hvveri version 5.1 */

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 

module claadd8s( A, B, CIN, SUM, COUT );
 input [7:0] A;
 input [7:0] B;
input CIN;
output COUT;
 output [7:0] SUM;
wire N_76;
wire N_77;
wire N_73;
wire N_74;
wire N_75;
wire N_1;
wire N_2;
wire N_3;
wire N_9;
wire N_10;
wire N_11;
wire N_12;
wire N_13;
wire N_14;
wire N_15;
wire N_16;
wire N_17;
wire N_18;
wire N_19;
wire N_20;
wire N_21;
wire N_22;
wire N_23;
wire N_24;
wire N_25;
wire N_26;
wire N_27;
wire N_28;
wire N_29;
wire N_31;
wire N_32;
wire N_33;
wire N_34;
wire N_35;
wire N_56;
wire N_60;
wire N_61;
wire N_68;
wire N_72;

or2i0 I_4 ( .A(N_74), .B(N_73), .Q(N_77) );
nor2i0 I_5 ( .A(N_74), .B(N_73), .Q(N_76) );
mux2x0 I_6 ( .A(N_76), .B(N_77), .Q(SUM[0]), .S(CIN) );
csac1 I_2 ( .A0(A[0]), .AB(N_73), .ABN(N_74), .B0(B[0]), .C1(N_75), .CIN(CIN) );
csalowc1 I_3 ( .A1(A[1]), .A1T(N_32), .B1(B[1]), .C0(N_29), .C0IN(N_75), .C1(N_31) );
xor2p QL49 ( .A(N_1), .B(N_11), .Q(SUM[4]) );
xor2p QL48 ( .A(N_10), .B(N_9), .Q(SUM[2]) );
csabitb QL47 ( .A(A[3]), .B(B[3]), .C0(N_3), .C1(N_2), .S0(N_35) );
csabitb QL46 ( .A(A[2]), .B(B[2]), .C0(N_34), .C1(N_33), .S0(N_9) );
csabita QL38 ( .A(A[7]), .B(B[7]), .C0(N_68), .C1(N_61), .S0(N_72) );
csabita QL37 ( .A(A[6]), .B(B[6]), .C0(N_60), .C1(N_56), .S0(N_16) );
csabita QL36 ( .A(A[5]), .B(B[5]), .C0(N_25), .C1(N_26), .S0(N_24) );
csabita QL35 ( .A(A[4]), .B(B[4]), .C0(N_28), .C1(N_27), .S0(N_11) );
buff QL34 ( .A(N_15), .Q(N_1) );
buff QL33 ( .A(N_31), .Q(N_10) );
muxc2dx2 QL32 ( .A(N_25), .B(N_26), .C(N_25), .D(N_26), .Q(N_20), .R(N_19),
             .S(N_27), .T(N_12) );
muxb2dx2 QL31 ( .A(N_25), .B(N_26), .C(N_25), .D(N_26), .Q(N_13), .R(N_21),
             .S(N_28), .T(N_14) );
mux4x6 QL27 ( .A(N_29), .B(N_29), .C(N_29), .D(N_29), .Q(SUM[1]), .S0(N_32),
           .S1(B[1]) );
csamuxd QL26 ( .A(N_24), .Q(SUM[5]), .S00(N_14), .S01(N_12), .S1(N_1) );
csamuxd QL25 ( .A(N_35), .Q(SUM[3]), .S00(N_34), .S01(N_33), .S1(N_10) );
csamuxc QL24 ( .A(N_3), .B(N_2), .Q(N_15), .S00(N_34), .S01(N_33), .S1(N_31) );
csamuxb QL22 ( .A(N_18), .B(N_17), .Q(COUT), .S00(N_21), .S01(N_19), .S1(N_15) );
csamuxb QL18 ( .A(N_23), .B(N_22), .Q(SUM[7]), .S00(N_13), .S01(N_20), .S1(N_1) );
csamuxa QL15 ( .A(N_16), .Q(SUM[6]), .S00(N_13), .S01(N_20), .S1(N_1) );
muxi2dx2 QL5 ( .A(N_72), .B(N_72), .C(N_68), .D(N_61), .Q(N_22), .R(N_17), .S(N_56) );
mux2dx2 QL1 ( .A(N_72), .B(N_72), .C(N_68), .D(N_61), .Q(N_23), .R(N_18), .S(N_60) );

endmodule // claadd8s


module or2i0( A, B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
wire N_1;
supply0 GND;
wire N_2;
supply1 VCC;

frag_f I_2 ( .F1(VCC), .F2(A), .F3(VCC), .F4(B), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m I_1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(VCC), .D2(GND), .E1(GND),
          .E2(VCC), .NS(N_1), .NZ(Q), .OS(N_2) );
frag_a QL3 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );

endmodule // or2i0


module nor2i0( A, B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(A), .A5(VCC), .A6(B), .AZ(Q) );

endmodule // nor2i0


module mux2x0( A, B, Q, S );
input A, B;
output Q;
input S;
parameter ql_gate = `LOGIC;
wire N_1;
supply1 VCC;
supply0 GND;
wire N_2;

frag_f I_2 ( .F1(S), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m I_1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(A), .D2(GND), .E1(B),
          .E2(GND), .NS(N_1), .NZ(Q), .OS(N_2) );
frag_a QL3 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );

endmodule // mux2x0


module csac1( A0, AB, ABN, B0, C1, CIN );
input A0;
output AB, ABN;
input B0;
output C1;
input CIN;
parameter ql_gate = `LOGIC;
supply0 GND;
supply1 VCC;

frag_m I_2 ( .B1(CIN), .B2(GND), .C1(VCC), .C2(GND), .D1(GND), .D2(VCC), .E1(GND),
          .E2(VCC), .NS(AB), .OS(ABN), .OZ(C1) );
frag_f I_1 ( .F1(VCC), .F2(GND), .F3(A0), .F4(GND), .F5(B0), .F6(GND), .FZ(AB) );
frag_a QL1 ( .A1(VCC), .A2(A0), .A3(VCC), .A4(B0), .A5(VCC), .A6(GND), .AZ(ABN) );

endmodule // csac1


module csalowc1( A1, A1T, B1, C0, C0IN, C1 );
input A1;
output A1T;
input B1;
output C0;
input C0IN;
output C1;
parameter ql_gate = `LOGIC;
supply0 GND;
supply1 VCC;

frag_m I_2 ( .B1(GND), .B2(VCC), .C1(B1), .C2(GND), .D1(B1), .D2(GND), .E1(VCC),
          .E2(GND), .NS(A1T), .OS(C0), .OZ(C1) );
frag_f I_1 ( .F1(A1), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(A1T) );
frag_a QL1 ( .A1(C0IN), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(C0) );

endmodule // csalowc1


module xor2p( A, B, Q );
input A, B;
output Q;
supply1 VCC;
supply0 GND;

mux4x0 QL1 ( .A(GND), .B(VCC), .C(VCC), .D(GND), .Q(Q), .S0(B), .S1(A) );

endmodule // xor2p


module csabitb( A, B, C0, C1, S0 );
input A, B;
output C0, C1, S0;
parameter ql_gate = `LOGIC;
supply0 GND;
supply1 VCC;

frag_m I_2 ( .B1(VCC), .B2(GND), .C1(GND), .C2(VCC), .D1(GND), .D2(VCC), .E1(GND),
          .E2(VCC), .NS(C1), .OS(C0), .OZ(S0) );
frag_f I_1 ( .F1(VCC), .F2(GND), .F3(VCC), .F4(B), .F5(VCC), .F6(A), .FZ(C1) );
frag_a QL1 ( .A1(A), .A2(GND), .A3(B), .A4(GND), .A5(VCC), .A6(GND), .AZ(C0) );

endmodule // csabitb


module csabita( A, B, C0, C1, S0 );
input A, B;
output C0, C1, S0;

and2i0 QL1 ( .A(A), .B(B), .Q(C0) );
nor2i0 QL2 ( .A(A), .B(B), .Q(C1) );
and2i2 QL3 ( .A(C0), .B(C1), .Q(S0) );

endmodule // csabita


module buff( A, Q );
input A;
output Q;
parameter ql_gate = `LOGIC;
supply0 GND;
supply1 VCC;

frag_a QL1 ( .A1(A), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(Q) );

endmodule // buff


module muxc2dx2( A, B, C, D, Q, R, S, T );
input A, B, C, D;
output Q, R;
input S;
output T;
parameter ql_gate = `LOGIC;
wire N_1;
supply0 GND;
supply1 VCC;

frag_m I_2 ( .B1(VCC), .B2(B), .C1(A), .C2(GND), .D1(VCC), .D2(D), .E1(C), .E2(GND),
          .NS(T), .NZ(R), .OS(N_1), .OZ(Q) );
frag_f I_1 ( .F1(S), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(T) );
frag_a QL1 ( .A1(GND), .A2(VCC), .A3(GND), .A4(VCC), .A5(GND), .A6(VCC), .AZ(N_1) );

endmodule // muxc2dx2


module muxb2dx2( A, B, C, D, Q, R, S, T );
input A, B, C, D;
output Q, R;
input S;
output T;
parameter ql_gate = `LOGIC;
wire N_1;
supply0 GND;
supply1 VCC;

frag_m I_2 ( .B1(A), .B2(GND), .C1(VCC), .C2(B), .D1(C), .D2(GND), .E1(VCC), .E2(D),
          .NS(T), .NZ(R), .OS(N_1), .OZ(Q) );
frag_f I_1 ( .F1(S), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(T) );
frag_a QL1 ( .A1(GND), .A2(VCC), .A3(GND), .A4(VCC), .A5(GND), .A6(VCC), .AZ(N_1) );

endmodule // muxb2dx2


module mux4x6( A, B, C, D, Q, S0, S1 );
input A, B, C, D;
output Q;
input S0, S1;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
supply1 VCC;
supply0 GND;

frag_a I_2 ( .A1(S1), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );
frag_f I_1 ( .F1(S0), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m QL3 ( .B1(A), .B2(GND), .C1(VCC), .C2(B), .D1(VCC), .D2(C), .E1(D), .E2(GND),
          .NS(N_1), .OS(N_2), .OZ(Q) );

endmodule // mux4x6


module csamuxd( A, Q, S00, S01, S1 );
input A;
output Q;
input S00, S01, S1;

mux4x6 QL1 ( .A(S00), .B(S00), .C(S01), .D(S01), .Q(Q), .S0(A), .S1(S1) );

endmodule // csamuxd


module csamuxc( A, B, Q, S00, S01, S1 );
input A, B;
output Q;
input S00, S01, S1;
wire N_1;

and2i1 QL1 ( .A(S1), .B(S01), .Q(N_1) );
mux4xe QL2 ( .A(A), .B(B), .C(B), .D(B), .Q(Q), .S0(N_1), .S1(S00) );

endmodule // csamuxc


module csamuxb( A, B, Q, S00, S01, S1 );
input A, B;
output Q;
input S00, S01, S1;
wire N_1;

and2i0 QL1 ( .A(S1), .B(S01), .Q(N_1) );
mux4x0 QL2 ( .A(A), .B(B), .C(B), .D(B), .Q(Q), .S0(N_1), .S1(S00) );

endmodule // csamuxb


module csamuxa( A, Q, S00, S01, S1 );
input A;
output Q;
input S00, S01, S1;

mux4xa QL1 ( .A(S00), .B(S00), .C(S01), .D(S01), .Q(Q), .S0(A), .S1(S1) );

endmodule // csamuxa


module muxi2dx2( A, B, C, D, Q, R, S );
input A, B, C, D;
output Q, R;
input S;

mux2dx1 QL1 ( .A(B), .B(A), .C(D), .D(C), .Q(Q), .R(R), .S(S) );

endmodule // muxi2dx2


module mux2dx2( A, B, C, D, Q, R, S );
input A, B, C, D;
output Q, R;
input S;
parameter syn_macro = 1, ql_pack = 1;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;
wire N_1;
wire N_2;

frag_a I_2 ( .A1(GND), .A2(VCC), .A3(GND), .A4(VCC), .A5(GND), .A6(VCC), .AZ(N_1) );
frag_f I_1 ( .F1(S), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_2) );
frag_m QL3 ( .B1(A), .B2(GND), .C1(VCC), .C2(B), .D1(C), .D2(GND), .E1(VCC), .E2(D),
          .NS(N_2), .NZ(R), .OS(N_1), .OZ(Q) );

endmodule // mux2dx2


module frag_f( F1, F2, F3, F4, F5, F6, FZ );
input F1, F2, F3, F4, F5, F6;
output FZ;
parameter ql_frag = 1;
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6;

endmodule // frag_f


module frag_m( B1, B2, C1, C2, D1, D2, E1, E2, NS, NZ, OS, OZ );
input B1, B2, C1, C2, D1, D2, E1, E2, NS;
output NZ;
input OS;
output OZ;
parameter ql_frag = 1;
 assign #1 NZ = NS ? (E1 & ~E2):(D1 & ~D2);
 assign #1 OZ = OS ? NZ:(NS ? (C1 & ~C2):(B1 & ~B2));

endmodule // frag_m


module frag_a( A1, A2, A3, A4, A5, A6, AZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
parameter ql_frag = 1;
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6;

endmodule // frag_a


module mux4x0( A, B, C, D, Q, S0, S1 );
input A, B, C, D;
output Q;
input S0, S1;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
supply1 VCC;
supply0 GND;

frag_a I_2 ( .A1(S1), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );
frag_f I_1 ( .F1(S0), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m QL3 ( .B1(A), .B2(GND), .C1(B), .C2(GND), .D1(C), .D2(GND), .E1(D), .E2(GND),
          .NS(N_1), .OS(N_2), .OZ(Q) );

endmodule // mux4x0


module and2i0( A, B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(A), .A2(GND), .A3(B), .A4(GND), .A5(VCC), .A6(GND), .AZ(Q) );

endmodule // and2i0


module and2i2( A, B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(A), .A5(VCC), .A6(B), .AZ(Q) );

endmodule // and2i2


module and2i1( A, B, Q );
input A, B;
output Q;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;

frag_a QL1 ( .A1(A), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(B), .AZ(Q) );

endmodule // and2i1


module mux4xe( A, B, C, D, Q, S0, S1 );
input A, B, C, D;
output Q;
input S0, S1;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
supply1 VCC;
supply0 GND;

frag_a I_2 ( .A1(S1), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );
frag_f I_1 ( .F1(S0), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m QL3 ( .B1(A), .B2(GND), .C1(VCC), .C2(B), .D1(VCC), .D2(C), .E1(VCC), .E2(D),
          .NS(N_1), .OS(N_2), .OZ(Q) );

endmodule // mux4xe


module mux4xa( A, B, C, D, Q, S0, S1 );
input A, B, C, D;
output Q;
input S0, S1;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
supply1 VCC;
supply0 GND;

frag_a I_2 ( .A1(S1), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );
frag_f I_1 ( .F1(S0), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_1) );
frag_m QL3 ( .B1(A), .B2(GND), .C1(VCC), .C2(B), .D1(C), .D2(GND), .E1(VCC), .E2(D),
          .NS(N_1), .OS(N_2), .OZ(Q) );

endmodule // mux4xa


module mux2dx1( A, B, C, D, Q, R, S );
input A, B, C, D;
output Q, R;
input S;
parameter syn_macro = 1, ql_pack = 1;
parameter ql_gate = `LOGIC;
supply1 VCC;
supply0 GND;
wire N_1;
wire N_2;

frag_a I_2 ( .A1(GND), .A2(VCC), .A3(GND), .A4(VCC), .A5(GND), .A6(VCC), .AZ(N_1) );
frag_f I_1 ( .F1(S), .F2(GND), .F3(VCC), .F4(GND), .F5(VCC), .F6(GND), .FZ(N_2) );
frag_m QL3 ( .B1(VCC), .B2(A), .C1(B), .C2(GND), .D1(VCC), .D2(C), .E1(D), .E2(GND),
          .NS(N_2), .NZ(R), .OS(N_1), .OZ(Q) );

endmodule // mux2dx1