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ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: D:\jtd\jtd.DSN Doc. no.: Revision: Author: Created: 07/07/25 Modified: 07/07/26 *PROPERTI

VERSION 6 BEGIN SCHEMATIC BEGIN ATTR DeviceFamilyName "spartan3e" DELETE all:0 EDITNAME all:0 EDITTRAIT all:0 END ATTR BEGIN NETLIST SIGNAL XLXN_50(

(PCB 2410_EXT (description (timeStamp "2004 01 05 07 55 40") (program "CAPTURE.EXE" (Version "9.10.157 CIS")) (source "Original data from OrCAD/CAPTURE schematic") (title "") (date "M

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: H:\Z\103\1616\1.DSN Doc. no.: Revision: Author: Created: 08/06/22 Modified: 08/10/0

(PCB LED (description (timeStamp "2004 01 13 06 17 46") (program "CAPTURE.EXE" (Version "9.00.1153 CIS")) (source "Original data from OrCAD/CAPTURE schematic") (title "") (date "星期四,

*PADS-LOGIC-V2005.2-CP936* DESIGN EXPORT FILE FROM PADS LOGIC V2007.0 *SCH* GENERAL PARAMETERS OF THE SCHEMATIC DESIGN" CUR SHEET 0 Current Active Sheet USERGRID 50

-- Vhdl instantiation template created from schematic top.sch - Thu Apr 06 09:31:43 2006 -- -- Notes: -- 1) This instantiation template has been automatically generated using types -- std_logic a

(PCB 2410_EXT (description (timeStamp "2004 01 05 07 55 40") (program "CAPTURE.EXE" (Version "9.10.157 CIS")) (source "Original data from OrCAD/CAPTURE schematic") (title "") (date "M

ProjNav -> New -> Test Fixture __projnav/createTF.err # ModelSim : Simulate Behavioral VHDL Model TEST_gate.fdo # ModelSim : Simulate Behavioral VHDL Model vsim.wlf # VHDL : Create Schematic Sym

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: C:\Documents and Settings\Administrator\桌面\3个IO口扫16键\ddd.DSN Doc. no.: Revision: Author: