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encoder_1553.prf
SCHEMATIC START ;
# map: version ispLever_v41_Production_Build_Classic (16c) -- Mon Jun 28 12:35:38 2004
SCHEMATIC END ;
#
# Logical Preferences generated for Lucent by Synplify 7.3.5, Build 26
test.cir
** Profile: "SCHEMATIC1-TEST" [ c:\documents and settings\bill\桌面\zhaojg\高频小信号\example-pspicefiles\schematic1\test.sim ]
** Creating circuit file "TEST.cir"
** WARNING: THIS AUTOMATICALLY GENER
test.out.1
**** 01/20/08 19:29:36 ******* PSpice 10.5.0 (Jan 2005) ******* ID# 2090009937
** Profile: "SCHEMATIC1-TEST" [ c:\documents and settings\bill\\zhaojg\\example-pspicefiles\schematic1\test.sim ]
test.out
**** 01/20/08 19:38:23 ******* PSpice 10.5.0 (Jan 2005) ******* ID# 2090009937
** Profile: "SCHEMATIC1-TEST" [ c:\documents and settings\bill\\zhaojg\\example-pspicefiles\schematic1\test.sim ]
bias.out.1
**** 01/20/08 14:29:07 ******* PSpice 10.5.0 (Jan 2005) ******* ID# 2090009937
** Profile: "SCHEMATIC1-bias" [ C:\Documents and Settings\Bill\\Zhaojg\LC\lc-pspicefiles\schematic1\bias.sim ]
bias.out
**** 01/20/08 18:28:03 ******* PSpice 10.5.0 (Jan 2005) ******* ID# 2090009937
** Profile: "SCHEMATIC1-bias" [ c:\documents and settings\bill\\zhaojg\lc\lc-pspicefiles\schematic1\bias.sim ]
bias.cir
** Profile: "SCHEMATIC1-bias" [ c:\documents and settings\bill\桌面\zhaojg\lc振荡器\lc-pspicefiles\schematic1\bias.sim ]
** Creating circuit file "bias.cir"
** WARNING: THIS AUTOMATICALLY GENERATED
__projnav.log
Project Navigator Auto-Make Log File
-------------------------------------
Started process "View RTL Schematic".
=========================================================================
*
__projnav.log
Project Navigator Auto-Make Log File
-------------------------------------
Started process "View RTL Schematic".
=========================================================================
*
tina.ini
[Schematic Editor]
DefSymbolSet=US
DefUnit=mm
AutoRepeat=0
AutoReWire=1
AppendValueToLabel=1