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andnor2.vf
// Verilog model created from schematic andnor2.sch - Wed Nov 13 17:04:16 2002
`timescale 1ns / 1ps
module andnor2(in1, in2, in3, in4, out_t);
input in1;
input in2;
input in3;
input
design1.opj
(ExpressProject "Design1"
(ProjectVersion "19981106")
(ProjectType "PCB")
(Folder "Design Resources"
(Folder "Library")
(NoModify)
(File ".\design1.dsn"
(Type "Schematic
lcd_top.pcf
//! **************************************************************************
// Written by: Map I.24 on Wed Aug 01 21:38:21 2007
//! ***************************************************************
usb2ide.rep
Protel Advanced Schematic Annotation Report D:\D12Smart\Cf_Mecopy\USB2IDE.REP 18:04:25 31-Aug-2000
CON? => CON1
U? => U1
R? => R1
R?
backup of sheet1.rep
Protel Advanced Schematic Annotation Report for 'Sheet1.Sch' 00:04:44 18-May-2005
R? => R4
R? => R5
R? => R6
R? => R7
R?
previous backup of sheet1.rep
Protel Advanced Schematic Annotation Report for 'Sheet1.Sch' 00:04:44 18-May-2005
R? => R4
R? => R5
R? => R6
R? => R7
R?
top.pcf
SCHEMATIC START ;
// created by map version G.28 on Thu Dec 02 09:28:27 2004
COMP "ps2data" LOCATE = SITE "P5" LEVEL 1;
COMP "sysclk" LOCATE = SITE "P80" LEVEL 1;
COMP "vsyncb" LOCATE = SITE
top.pcf
SCHEMATIC START ;
// created by map version G.28 on Thu Dec 02 09:30:10 2004
COMP "ps2data" LOCATE = SITE "P5" LEVEL 1;
COMP "sysclk" LOCATE = SITE "P80" LEVEL 1;
COMP "vsyncb" LOCATE = SITE
clock.pcf
SCHEMATIC START ;
// created by map version G.28 on Thu Dec 02 09:21:35 2004
COMP "en" LOCATE = SITE "P205" LEVEL 1;
COMP "clk" LOCATE = SITE "P80" LEVEL 1;
COMP "seg" LOCATE = SITE "P16"
binarycounter.pcf
//! **************************************************************************
// Written by: Map I.27 on Sat Oct 07 16:25:32 2006
//! ***************************************************************