andnor2.vf

Xinx ISE 官方源代码盘第二章

// Verilog model created from schematic andnor2.sch - Wed Nov 13 17:04:16 2002


`timescale 1ns / 1ps

module andnor2(in1, in2, in3, in4, out_t);

 input in1;
 input in2;
 input in3;
 input in4;
output out_t;

wire XLXN_8;
wire XLXN_9;

AND2 XLXI_1 (.I0(in2), .I1(in1), .O(XLXN_8));
AND2 XLXI_3 (.I0(in4), .I1(in3), .O(XLXN_9));
NOR2 XLXI_2 (.I0(XLXN_9), .I1(XLXN_8), .O(out_t));
endmodule