代码搜索：Scan

找到约 10,000 项符合「Scan」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/148570/12457381

asm isr.asm

.INCLUDE hardware.inc .EXTERNAL F_Key_Scan; .external _h; .external _x; .external _Filter_LED_Show .external _temp1,_temp2,_mytemp; .external _feeddog .TEXT //键盘扫描与了LED显示中断 .PUBLIC _IRQ6;
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www.eeworm.com/read/336271/12460302

eqn i2c.map.eqn

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o
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www.eeworm.com/read/129953/14215972

h key.h

#ifndef __KEY_H__ #define __KEY_H__ #define aVKEY (*(volatile unsigned *)0x4000000) #define aHKEY (*(volatile unsigned *)0x4000000) U8 Key_Scan(void); U8 Get_Key(void); #endif /*__KEY_H__*
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www.eeworm.com/read/230799/14273791

uv2 bjdj.uv2

### uVision2 Project, (C) Keil Software ### Do not modify ! Target (Target 1), 0x0000 // Tools: 'MCS-51' Group (Source Group 1) File 1,1, 0x0 File 1,1,
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www.eeworm.com/read/230799/14273793

bak bjdj_uv2.bak

### uVision2 Project, (C) Keil Software ### Do not modify ! Target (Target 1), 0x0000 // Tools: 'MCS-51' Group (Source Group 1) File 1,1, 0x0 File 1,1,
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www.eeworm.com/read/226935/14446619

c block.c

/*! ************************************************************************************* * \file block.c * * \brief * Process one block * * \author * Main contributors (see co
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www.eeworm.com/read/223128/14654949

tspec dial1.tspec

AUTO_TS_P2P:FROM:clk:TO:en:1 AUTO_TS_F2P:FROM:en_xhdl.Q:TO:en:1 AUTO_TS_F2P:FROM:cnt_scan.Q:TO:en:1 AUTO_TS_P2P:FROM:clk:TO:en:1 AUTO_TS_F2P:FROM:en_xhdl.Q:TO:en:1 AUTO_T
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www.eeworm.com/read/223128/14655225

htm timing_report.htm

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www.eeworm.com/read/214502/15098332

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity song is port( clk : in vl_logic; speaker : out vl_logic; index : in vl_logic_vect
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www.eeworm.com/read/211745/15174580

vhd codetran.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity codetran is port(scan_code :in std_logic_vector(7 downto 0); clk:in std_logic;
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