代码搜索:STM32寄存器

找到约 10,000 项符合「STM32寄存器」的源代码

代码结果 10,000
www.eeworm.com/read/32339/1033944

vhd 8位寄存器.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG IS PORT(D:IN STD_LOGIC_VECTOR(0 TO 7); //定义一组8个D触发器 CLK:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(0 TO 7)); END
www.eeworm.com/read/38884/1117541

vhd 8位寄存器.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG IS PORT(D:IN STD_LOGIC_VECTOR(0 TO 7); //定义一组8个D触发器 CLK:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(0 TO 7)); END
www.eeworm.com/read/39475/1131986

vhd 8位寄存器.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG IS PORT(D:IN STD_LOGIC_VECTOR(0 TO 7); //定义一组8个D触发器 CLK:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(0 TO 7)); END
www.eeworm.com/read/355003/3070240

ewb 移位寄存器.ewb

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: "" EncryptionType: 2 UsingVectorGraphics: 0 /000@D0I0?4D
www.eeworm.com/read/414829/11101005

vi 4位寄存器.vi

www.eeworm.com/read/414829/11101050

vi 4位寄存器.vi

www.eeworm.com/read/268989/11112314

v 12位寄存器.v

// User-Defined Macrofunction // download from: http://www.fpga.com.cn module reg12 ( d, clk, q); input [11:0]d; input clk; output [11:0]q; reg [11:0]q; always @(posedge clk)
www.eeworm.com/read/105419/15667676

txt 寄存器传输格式.txt

; stmfd sp!,{lr,pc,r0-r2} ; mov r0,sp ; mrs r1,cpsr ; mrs r2,spsr ; stmfd sp!,{r0-r12} ; MOV R0, #Mode_USR:OR:I_Bit:OR:F_Bit ; No