代码搜索：STD_LOGIC_ARITH
找到约 548 项符合「STD_LOGIC_ARITH」的源代码
代码结果 548
www.eeworm.com/read/355654/10251377
mti test.cr.mti
D:/8051/i8051_dec.vhd {1 {vcom -work work -2002 -explicit -vopt D:/8051/i8051_dec.vhd
Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
-- Loading package standard
-- Loading pack
www.eeworm.com/read/459160/7279585
mti division.cr.mti
C:/Modeltech_6.0/examples/division/div8.vhd {1 {vcom -work work -2002 -explicit C:/Modeltech_6.0/examples/division/div8.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Load
www.eeworm.com/read/324197/13279285
mti cpu.cr.mti
C:/TDDOWNLOAD/cpudisgn/cpusample/cpu.vhd {1 {vcom -work work -2002 -explicit -novopt C:/TDDOWNLOAD/cpudisgn/cpusample/cpu.vhd
Model Technology ModelSim SE vcom 6.1f Compiler 2006.05 May 12 2006
-- L
www.eeworm.com/read/487358/6509202
cpp xsimtestbench_arch.cpp
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#ifdef __MINGW32__
#include "xsimMinGW.h"
#else
#include "xsim.h"
#endif
#include "C:/Xilinx92i
www.eeworm.com/read/252132/12300368
vhd compare.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY compare IS
PORT ( A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
www.eeworm.com/read/223600/14622468
mti cpunew2.cr.mti
C:/CPUNEW/top.vhd {1 {vcom -work work -2002 -explicit C:/CPUNEW/top.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1
www.eeworm.com/read/415793/11053663
vhd compare.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY compare IS
PORT ( A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
www.eeworm.com/read/167697/9955509
vhd 无符号数到整数的转换.vhd
-- Conversion Function
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY adder IS
PORT (op1, op2 : IN U
www.eeworm.com/read/164962/10080391
vhd conversion_altera.vhd
-- MAX+plus II VHDL Example
-- Conversion Function
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE i
www.eeworm.com/read/422532/10631558
vhd adder.vhd
-- MAX+plus II VHDL Example
-- Conversion Function
-- Copyright (c) 1994 Altera Corporation
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY adder IS
PORT (o