代码搜索：SOUT

找到约 712 项符合「SOUT」的源代码

代码结果 712
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/141319/13023055

ini suart.ini

load 8051.dll load SUART xtal=11059200 mode com1 1200 assign com1 sout g,main ws TL0
·
www.eeworm.com/read/137001/13348408

ini suart.ini

load 8051.dll load SUART xtal=11059200 mode com1 1200 assign com1 sout g,main ws TL0
·
www.eeworm.com/read/321656/13401262

ini suart.ini

load 8051.dll load SUART xtal=11059200 mode com1 1200 assign com1 sout g,main ws TL0
·
www.eeworm.com/read/347103/11700049

ini suart.ini

load 8051.dll load SUART xtal=11059200 mode com1 1200 assign com1 sout g,main ws TL0
·
www.eeworm.com/read/175784/9532360

hier_info enc_dec.hier_info

|enc_dec sout0 reg_exchange:inst1.clk clk => ACS_0:inst3.clk clk => ACS_2:inst5.clk clk => ACS_1:inst4.clk clk => tr_dff2:inst2.clk clk => conv_213:inst.clk
·
www.eeworm.com/read/437667/7744001

hier_info enc_dec.hier_info

|enc_dec sout0 reg_exchange:inst1.clk clk => ACS_0:inst3.clk clk => ACS_2:inst5.clk clk => ACS_1:inst4.clk clk => tr_dff2:inst2.clk clk => conv_213:inst.clk
·
www.eeworm.com/read/321790/13398977

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity carry_sum is port( sin : in vl_logic; cin : in vl_logic; sout : out vl_logic
·
www.eeworm.com/read/14022/292111

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity carry_sum is port( sin : in vl_logic; cin : in vl_logic; sout : out vl_logic
·
www.eeworm.com/read/17761/756488

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity carry_sum is port( sin : in vl_logic; cin : in vl_logic; sout : out vl_logic
·
www.eeworm.com/read/17761/756793

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity carry_sum is port( sin : in vl_logic; cin : in vl_logic; sout : out vl_logic
·