_primary.vhd

来自「SDRAM 控制器」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity carry_sum is
    port(
        sin             : in     vl_logic;
        cin             : in     vl_logic;
        sout            : out    vl_logic;
        cout            : out    vl_logic
    );
end carry_sum;