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Remote Control 的代码
ram_control.v
module ram_control(q,clk,rst);
input clk,rst;
output [3:0] q;
wire [3:0] q;
reg [3:0] data;
reg wren;
reg [3:0] wraddress;
reg [3:0] rdaddress;
reg [4:0] countwr;
reg [1:0] s
control_display.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_display is
Port (clk : in std_logic; -- 1khz;
start :
vga_control.c
/**************************************************************
程序说明 :VGA显示控制器测试
类 型 :Nios II
作 者 :
公 司 :杭州自由电子科技
:http://www.freefpga.com
电 话 :0
control_interface.v
/******************************************************************************
*
* LOGIC CORE: Control Interface - Top level module
* MODULE NAME: control_interface()
* COM
phase_control.bdf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
osc_control.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
osc_control.v
module osc_control(
oscaddrin,
oscdatain,
osc_sig,
cs,
clk,
ADDROUT,
DATAOUT,
rden,
wren
);
input [16:0] oscaddrin;
input [15:0] oscd
osc_control.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to