osc_control.bsf

verilog编写基于FPGA的示波器核心实现

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 232 144)
	(text "osc_control" (rect 5 0 61 12)(font "Arial" ))
	(text "inst" (rect 8 112 25 124)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "oscaddrin[16..0]" (rect 0 0 79 12)(font "Arial" ))
		(text "oscaddrin[16..0]" (rect 21 27 100 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 3))
	)
	(port
		(pt 0 48)
		(input)
		(text "oscdatain[15..0]" (rect 0 0 79 12)(font "Arial" ))
		(text "oscdatain[15..0]" (rect 21 43 100 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 3))
	)
	(port
		(pt 0 64)
		(input)
		(text "osc_sig" (rect 0 0 37 12)(font "Arial" ))
		(text "osc_sig" (rect 21 59 58 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 1))
	)
	(port
		(pt 0 80)
		(input)
		(text "cs" (rect 0 0 11 12)(font "Arial" ))
		(text "cs" (rect 21 75 32 87)(font "Arial" ))
		(line (pt 0 80)(pt 16 80)(line_width 1))
	)
	(port
		(pt 0 96)
		(input)
		(text "clk" (rect 0 0 14 12)(font "Arial" ))
		(text "clk" (rect 21 91 35 103)(font "Arial" ))
		(line (pt 0 96)(pt 16 96)(line_width 1))
	)
	(port
		(pt 216 32)
		(output)
		(text "ADDROUT[9..0]" (rect 0 0 80 12)(font "Arial" ))
		(text "ADDROUT[9..0]" (rect 115 27 195 39)(font "Arial" ))
		(line (pt 216 32)(pt 200 32)(line_width 3))
	)
	(port
		(pt 216 48)
		(output)
		(text "DATAOUT[7..0]" (rect 0 0 76 12)(font "Arial" ))
		(text "DATAOUT[7..0]" (rect 119 43 195 55)(font "Arial" ))
		(line (pt 216 48)(pt 200 48)(line_width 3))
	)
	(port
		(pt 216 64)
		(output)
		(text "rden" (rect 0 0 21 12)(font "Arial" ))
		(text "rden" (rect 174 59 195 71)(font "Arial" ))
		(line (pt 216 64)(pt 200 64)(line_width 1))
	)
	(port
		(pt 216 80)
		(output)
		(text "wren" (rect 0 0 22 12)(font "Arial" ))
		(text "wren" (rect 173 75 195 87)(font "Arial" ))
		(line (pt 216 80)(pt 200 80)(line_width 1))
	)
	(parameter
		"IDLE"
		"B\"0001\""
		""
	)
	(parameter
		"ALLIN"
		"B\"0010\""
		""
	)
	(parameter
		"WAIT1"
		"B\"0100\""
		""
	)
	(parameter
		"WAIT2"
		"B\"1000\""
		""
	)
	(drawing
		(rectangle (rect 16 16 200 112)(line_width 1))
	)
	(annotation_block (parameter)(rect 232 -64 332 16))
)