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Regulator 的代码
readme.txt
****************************************************************************************************
ADSP-BF561 EZ-KIT
Voltage Regulator Example
Analog Devices, Inc.
DSP Division
Three Tec
bf561_regulator_basiccrt.s
/* MANAGED-BY-SYSTEM-BUILDER */
/*
** BF561_Regulator_basiccrt.s generated on May 26, 2006 at 00:16:46.
**
** Copyright (C) 2000-2006 Analog Devices Inc., All Right
bf561_regulator_heaptab.c
/* MANAGED-BY-SYSTEM-BUILDER */
/*
** User heap source file generated on May 26, 2006 at 00:16:46.
**
** Copyright (C) 2000-2006 Analog Devices Inc., All Rights Res
regulator 1-2_sch.prp
("FILE_TYPE" "PMAP File"
("devices"
("VDC")
("Q2N2222"
("info"
("spice_dsg" "X")
)
("model_params"
("lev
regulator stepped rload_sch.prp
("FILE_TYPE" "PMAP File"
("devices"
("E")
("VDC")
("R"
("info"
("spice_dsg" "R")
("port_order"
("1")
regulator stepped rload no comp.als
.ALIASES
E_E1 E1(3=N18299 4=0 1=N18367 2=N18253 ) CN @CHAPTER 1.Regulator stepped Rload(sch_1):INS18303@ANALOG.E.Normal(chips)
V_Vref Vref(+=N18367 -=0 ) CN @CHAPTER 1.Regulator
regulator 2 stepped vin.als
.ALIASES
E_E2 E2(OUT+=N17769 OUT-=0 IN1+=N17705 IN1-=0 IN2+=N17439 IN2-=0 ) CN @CHAPTER 1.Regulator 2 stepped
+Vin(sch_1):INS17631@ABM.ESUM.Normal(chips)
E_GAIN1 GAIN1(OUT=N1770
regulator 2 stepped vin.prb
[DISPLAYS]
BEGIN DISPLAY LAST SESSION
ANALYSIS TRANSIENT_ANALYSIS
SYMBOL ALWAYS
TRACECOLORSCHEME NORMAL
BEGIN ANAPLOT 1
ACTIVE
XBASE
BEGIN XAXIS
XAXISUSERNAME 0 (null)
RANGEFLAG AUTO
TYPE L