readme.txt

analog device vdsp dynamic power control tutorial

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ADSP-BF561 EZ-KIT 

Voltage Regulator Example

Analog Devices, Inc.
DSP Division
Three Technology Way
Norwood, MA 02062

Date Created:	11/24/03

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This example modifies the internal voltage regulator and PLL registers to demonstrate the dynamic
power management capabilities of the BF561.  The 4 push-buttons (SW6-9) are interrupt sources used
to increment/decrement the on-chip regulator voltage.  Both cores perform simple blink routines
using delay loops.  LEDs 17-20 are modified by core A while LEDs 13-16 are modified by Core B.
Activity on LEDs 5-12 is Core A displaying the current VLEV value in the VR_CTL register after the
increment/decrement is performed.

This is a dual core project. Please see section III to get familiar with the project structure.
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CONTENTS

I.	 FUNCTIONAL DESCRIPTION
II.	 OPERATION DESCRIPTION
III. 	 PROJECT STRUCTURE


I.    FUNCTIONAL DESCRIPTION

	The Regulator example demonstrates the modification of the VR_CTL register (specifically, the
	VLEV field), the method to configure flags as interrupts, the ability to switch Core frequency
	on-the-fly to work with whatever new voltage level is being programmed in the internal regulator,
	and the use of the Supplemental Interrupts to signal one core from the other to perform a
	specific task.

	Core A initializes the LEDs as outputs and the push-buttons as interrupt inputs.  It also
	configures and registers interrupt routines.  Core A then runs a blink routine on LEDs 17-20.
	Pressing SW6 or SW7 decrements the internal regulator voltage by 50mV.  Once the sensed VLEV
	value goes under 1.0V, the VCO is modified to CCLK=VCO/2 in order to prevent overclocking at low
	power.  Pressing SW8 or SW9 increments the internal regulator voltage by 50mV.  Once the sensed
	VLEV value is near 1.0V, the VCO is set to the default of CCLK=VCO/1.  In the flag interrupt
	routines, Core A asserts the Core B Supplemental Interrupt 0 to signal Core B that it must go to
	idle for the forthcoming write to VR_CTL.

	Core B configures and registers an interrupt routine for the Supplemental Interrupt 0.  Core B
	then runs a blink routine on LEDs 13-16 while waiting for the Supplemental Interrupt to be raised
	by Core A, at which point Core B goes to idle.  Both cores must be in idle for the VR_CTL wake-up
	to apply the changes made to the VLEV field.
	

II.  OPERATION DESCRIPTION

	- Open the "BF561_Regulator.dpg" project group in the VisualDSP Integrated
	  Development Environment (IDDE). Follow instructions in section III.
	  
	- Under the "Project" tab, select "Build Project" (program is then loaded automatically into DSP).

	- Dipswitch SW4: set #1, 2, 3, 4 to "on", all others to "off"
	
	- Run the executables by pressing "multiprocessor run" (CTRL-F5) on the toolbar. DO NOT use the
	  single core (F5) button.  You should see LED activity on LEDs 13-20 corresponding to the two
	  blink routines running on the cores.
	  
	- Push SW8/SW9: LEDs 5-8 show the newly incremented VLEV value in VR_CTL (range = 0x3-0xF)
		- Once it reaches the max 0xF, pushing this button has no effect
		- If the former VLEV field was 0x7, the LEDs 13-20 blink faster due to the increased CCLK
		- Probe the test-point (TP7, near the hole in the center of the board) to measure the voltage
		  being applied to the core via the internal regulator.

	- Push SW6/SW7: LEDs 5-8 show the newly decremented VLEV value in VR_CTL (range = 0x3-0xF)
		- Once it reaches the min 0x3, pushing this button has no effect
		- If the former VLEV field was 0x9, the LEDs 13-20 blink slower due to the decreased CCLK
	  
	- The main header file "BF561_Regulator.h" contains #define statements for all of the project
	  constants.  It also initializes all function prototypes and interrupt handlers and includes
	  shared library header files.

		
III. PROJECT STRUCTURE

	This is a dual core project. It consists of a main project - containing only system defines and
        linker settings-
			".\BF561_Regulator.dpj",	
	four sub-projects 		- containing the source code -
			".\core A\Core_A.dpj"					( code exclusive to core A, in L1 memory)
			".\core B\core_B.dpj"					( code exclusive to core B, in L1 memory)
			".\Shared Memory L2\SM_L2.dpj"			( code that is shared between the cores, in on-chip L2 memory)
			".\Shared Memory L3\SM_L3.dpj" 			( code that is shared between the cores, in off-chip L3 memory, SDRAM),
	and the project group file that ties everything together:
			".\BF561_Regulator.dpg".
			
	Follow this procedure to open and compile the project:
	- open the project group (File-> Open-> Project Group)
	- Right click on the main project and re-build the project.