代码搜索：RISC
找到约 3,488 项符合「RISC」的源代码
代码结果 3,488
www.eeworm.com/read/102935/6228368
c bttv-risc.c
/*
bttv-risc.c -- interfaces to other kernel modules
bttv risc code handling
- memory management
- generation
(c) 2000 Gerd Knorr
This program is
www.eeworm.com/read/101042/6258245
s pa-risc.s
.SPACE $PRIVATE$
.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
.SPACE $TEXT$
.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
.SUBSPA $CODE$,QUAD=0,ALIGN=8,AC
www.eeworm.com/read/100503/6268850
s pa-risc.s
.SPACE $PRIVATE$
.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
.SPACE $TEXT$
.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
.SUBSPA $CODE$,QUAD=0,ALIGN=8,AC
www.eeworm.com/read/100037/6276160
s pa-risc.s
.SPACE $PRIVATE$
.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
.SPACE $TEXT$
.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
.SUBSPA $CODE$,QUAD=0,ALIGN=8,AC
www.eeworm.com/read/410306/11293993
mpf risc_cpu.mpf
; Copyright 1991-2008 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION
www.eeworm.com/read/406292/11444996
gif risc8.gif
www.eeworm.com/read/261865/11618028
v risc_core.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Mini-RISC-1
www.eeworm.com/read/158146/11642026
v risc_cpu.v
//******************cpu.v*****************
module cpu(clk,rst,data_in,data_out,read,write,addr,halt);
output [15:0] data_out;
output [15:0] addr;
output read,write,halt;
input [15:0]data_in;
inp
www.eeworm.com/read/258646/11848217
v risc_spm.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|16 Jul 2001 18:46:12 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{980A4893-B92C-420D-886C-E9D7B862C22F}
vti_cacheddtm:TX|16 Jul 2001 18
www.eeworm.com/read/258646/11848227
v risc_spm.v
module RISC_SPM (clk, rst);
parameter word_size = 8;
parameter Sel1_size = 3;
parameter Sel2_size = 2;
wire [Sel1_size-1: 0] Sel_Bus_1_Mux;
wire [Sel2_size-1: 0] Sel_Bus_2_Mux;
inp