代码搜索:Processor
找到约 10,000 项符合「Processor」的源代码
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www.eeworm.com/read/163678/10150305
cpp processor.cpp
//FILE:processor.cpp (systemc)
//# vim600:sw=2:tw=0:fdm=marker
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//See processor.h for more information
//~~~~~~~~~~~~~~~~
www.eeworm.com/read/162587/10294838
h processor.h
/*************************************************************************
Copyright (c) 1999 Mentor Graphics Corporation.
IMPORTANT - USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS
www.eeworm.com/read/425636/10343279
h processor.h
#include
#if __CODEVISIONAVR__ < 1255
#error Minimume CodevisionAVR requered ver is: 1.25.5
#endif
#define TINY_FAT 1 /* 0 means use FULL FAT firmware for Large memory systems wit
www.eeworm.com/read/425636/10343328
h~ processor.h~
#include
#if __CODEVISIONAVR__ < 1255
#error Minimume CodevisionAVR requered ver is: 1.25.5
#endif
#define TINY_FAT 1 /* 0 means use FULL FAT firmware for Large memory systems with
www.eeworm.com/read/425622/10343973
h processor.h
#include
#if __CODEVISIONAVR__ < 1255
#error Minimume CodevisionAVR requered ver is: 1.25.5
#endif
#define TINY_FAT 1 /* 0 means use FULL FAT firmware for Large memory systems with
www.eeworm.com/read/425622/10344046
h~ processor.h~
#include
#if __CODEVISIONAVR__ < 1255
#error Minimume CodevisionAVR requered ver is: 1.25.5
#endif
#define TINY_FAT 1 /* 0 means use FULL FAT firmware for Large memory systems with
www.eeworm.com/read/278377/10540211
h processor.h
//*************************************************************************
// ADVANCED DIGITAL IMAGING SOLUTIONS LABORATORY
//
// Processor.h : interface to Processor.cpp
// Date : January 06, 20
www.eeworm.com/read/278377/10540218
cpp processor.cpp
//*************************************************************************
// ADVANCED DIGITAL IMAGING SOLUTIONS LABORATORY
//
// Processor.cpp : implementation file
// Date : January 06, 2006
/
www.eeworm.com/read/420236/10809939
v processor.v
module processor(clock, reset, enter, halt, input1, output1);
input clock;
input reset;
input enter;
input [15:0]input1;
output halt;
reg halt;
output[15:0]output1;
reg [15:0]output1;
reg [3: