processor.v

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module processor(clock, reset, enter, halt, input1, output1);
input clock;
input reset;
input enter;
input [15:0]input1;
output halt;
reg halt;
output[15:0]output1;
reg [15:0]output1;
reg [3:0]state;
reg[15:0]IR;
reg[4:0]PC;
reg[15:0]A;
reg[4:0]memory_address;
reg[15:0]memory_data;
reg wren;
`define s_start 0
`define s_fetch 1
`define s_decode 2
`define s_load 3
`define s_add 4
`define s_sub 5
`define s_mul 6
`define s_div 7
`define s_and 8
`define s_or 9
`define s_not 10
`define s_jz  11
`define s_jpos 12
`define s_in 13
`define s_store 14
`define s_halt 15
//parameter DATA_WIDTH = 16;
//parameter ADDR_WIDTH = 5;
	//reg [DATA_WIDTH-1:0]memory_data[2**ADDR_WIDTH-1:0];
ram reg1(
.address(memory_address),
.clock(clock),
.data(A),
.wren(wren),
.q(memory_data)
);
	//initial
	//begin
		//$readmemb("program1.txt", memory_data);
	//end
always @(posedge clock or negedge reset)
begin
if (~reset) begin
			PC=5'b0;
			IR=16'b0;
			A=16'b0;
			halt=1'b0;
			output1 <= A;
			//$readmemb("program1.txt", memory_data);
			state = `s_start;
			end
else 	begin
			case (state)
				`s_start: 
					begin
					memory_address = PC;
					state = `s_fetch;
					end
				`s_fetch:
					begin
					IR = memory_data;
					PC = PC + 5'b1;
					state = `s_decode;
					end
				`s_decode:
					begin
					memory_address = IR[4:0];
					case (IR[15:12])
					4'b0011: state = `s_store;
					4'b0100: state = `s_load;
					4'b0101: state = `s_add;
					4'b0110: state = `s_sub;
					4'b0111: state = `s_mul;
					4'b1000: state = `s_div;
					4'b1001: state = `s_and;
					4'b1010: state = `s_or;
					4'b1011: state = `s_not;
					4'b1100: state = `s_jz;
					4'b1101: state = `s_jpos;
					4'b1110: state = `s_in;
					4'b1111: state = `s_halt;
					default: state = `s_start;
					endcase
					end
				`s_load:
					begin
					A = memory_data;
					output1 <= A;
					state = `s_start;
					end
				`s_add:
					begin
					A = A + memory_data;
					output1 <= A;
					state = `s_start;
					end
				`s_sub:
					begin
					A = A - memory_data;
					output1 <= A;
					state = `s_start;
					end
				`s_mul:
					begin
					A = A * memory_data;
					output1 <= A;
					state = `s_start;
					end
				`s_div:
					begin
					A = A / memory_data;
					output1 <= A;
					state = `s_start;
					end
				`s_in:
					begin
					A = input1;
					output1 <= A;
					if (enter == 1) state = `s_in;
					else state = `s_start;
					end
				`s_store:
					begin
					wren = 1'b1;
					//memory_data = A;
					state = `s_start;
					end
				`s_and:
					begin
					A = A & memory_data;
					output1 <= A;
					state = `s_start;
					end
				`s_or:
					begin
					A = A | memory_data;
					output1 <= A;
					state = `s_start;
					end
				`s_not:
					begin
					A = ~A;
					output1 <= A;
					state = `s_start;
					end
				`s_jz:
					begin
					if (A == 16'b0) PC = IR[4:0];
					state <= `s_start;
					end
				`s_jpos:
					begin
					if (A > 0) PC = IR[4:0];
					state <= `s_start;
					end
				`s_halt:
					begin
					halt = 1'b1;
					state = `s_halt;
					end
				default:
					state = `s_halt;
			endcase
		end
end
endmodule