代码搜索：Process
找到约 10,000 项符合「Process」的源代码
代码结果 10,000
www.eeworm.com/read/149929/12330884
vhd demo.vhd
--MOORE 状态机设计--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--*********************
ENTITY demo IS
PORT(
clk,in1,reset: IN std_logic;
out1: OUT std_logic_vector(3 downto 0));
END de
www.eeworm.com/read/149929/12331035
vhd half51.vhd
library ieee;
use ieee.std_logic_1164.all; --库定义
--*************************--
ENTITY half51 IS
PORT(a,b: in bit;
s,c:out);
END ;
www.eeworm.com/read/149929/12331202
vhd clkgen.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY clkgen IS
PORT (
clk : IN STD_LOGIC;
newclk : OUT STD_LOGIC
);
END clkgen;
ARCHITECTURE A OF clkgen IS
SI
www.eeworm.com/read/149929/12331368
vhd ggg.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GGG IS
PORT(d0,d1,sel:IN BIT;
q:OUT BIT);
END GGG;
ARCHITECTURE connect OF GGG IS
SIGNAL tmp:BIT;
BEGIN
cale:PROCESS(d0,d1,sel)
VARIABLE
www.eeworm.com/read/149929/12332671
vhd demo.vhd
--MOORE 状态机设计--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--*********************
ENTITY demo IS
PORT(
clk,in1,reset: IN std_logic;
out1: OUT std_logic_vector(3 downto 0));
END de
www.eeworm.com/read/149929/12333002
vhd half51.vhd
library ieee;
use ieee.std_logic_1164.all; --库定义
--*************************--
ENTITY half51 IS
PORT(a,b: in bit;
s,c:out);
END ;
www.eeworm.com/read/149929/12333024
vhd ggg.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GGG IS
PORT(d0,d1,sel:IN BIT;
q:OUT BIT);
END GGG;
ARCHITECTURE connect OF GGG IS
SIGNAL tmp:BIT;
BEGIN
cale:PROCESS(d0,d1,sel)
VARIABLE
www.eeworm.com/read/149929/12333166
vhd demo.vhd
--MOORE 状态机设计--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--*********************
ENTITY demo IS
PORT(
clk,in1,reset: IN std_logic;
out1: OUT std_logic_vector(3 downto 0));
END de
www.eeworm.com/read/149908/12334415
h proc.h
#ifndef _PROC_H
#define _PROC_H
#include
#ifndef _MBUF_H
#include "mbuf.h"
#endif
#ifndef _TIMER_H
#include "timer.h"
#endif
#define SIGQSIZE 200 /* Entries in ksignal queu
www.eeworm.com/read/149907/12334534
plg test.plg
礦ision2 Build Log
Project:
E:\Electronic\Keil uVision\Design\TestSerial\Test.uv2
Project File Date: 01/05/2006
Output:
Build target 'Target 1'