clkgen.vhd

来自「大家一定要看 哦 程序在与多看多练 我找了好久才找到呢」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY clkgen IS
 PORT (
          clk : IN STD_LOGIC;
           newclk : OUT  STD_LOGIC
       );
END clkgen;
ARCHITECTURE A OF clkgen IS
      SIGNAL TEMP :integer range 0 to 16#752f#;
BEGIN
   process(clk)
     begin
       if clk'event and clk='1' then
          if temp=16#752f# then temp<=0;
          else temp<=temp+1;
          end if;
       end if;
     end process;
   process(temp)
      begin
          if temp=16#752f# then  newclk<='1';
          else newclk<='0';
          end if;
    end process;

END A;