代码搜索：Process
找到约 10,000 项符合「Process」的源代码
代码结果 10,000
www.eeworm.com/read/252132/12300601
vhd rege.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY rege IS
PORT ( R, Resetn, E, Clock : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC ) ;
END rege ;
ARCHITECTURE Behavior OF rege IS
BEG
www.eeworm.com/read/252132/12300620
vhd downcnt.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY downcnt IS
GENERIC ( modulus : INTEGER := 8 ) ;
PORT ( Clock, L, E : IN STD_LOGIC ;
Q : OUT INTEGER RANGE 0 TO modulus-1 ) ;
END d
www.eeworm.com/read/252132/12300636
vhd bitcount.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY work ;
USE work.components.shiftrne ;
ENTITY bitcount IS
PORT( Clock, Resetn : IN STD_LOGIC ;
LA, s : IN STD_LOGIC ;
Data
www.eeworm.com/read/251907/12312150
tcp videogenerator.tcp
---- Checkpoint Tool Report File ----
*********************************
Par checkpoint failed.
Design does not meet timing.
*********************************
Process Continuing ...
www.eeworm.com/read/150072/12317082
cpp d10r1.cpp
#include
#include
#include
#include
double func(double x)
{
double t;
t=bessj0( x);
return t;
}
void main()
{
//program d10r1
www.eeworm.com/read/150027/12324794
java core.java
class Core{double d;
Core(String s)
{
StringProcess sp=new StringProcess();
StringBuffer sb=new StringBuffer();
sb=sp.replace(s);
InitPush ip=new InitPush(sb.toString());
ip.process();
www.eeworm.com/read/149999/12325925
vhd counter.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Counter is
port
(clk1,clk2:in std_logic; --clk1为待计数信号，clk2为计数时钟
result1,result2,result3:out integer range 0 to 9;
over,low:out std_logi
www.eeworm.com/read/149929/12330494
vhd half51.vhd
library ieee;
use ieee.std_logic_1164.all; --库定义
--*************************--
ENTITY half51 IS
PORT(a,b: in bit;
s,c:out);
END ;
www.eeworm.com/read/149929/12330515
vhd ggg.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GGG IS
PORT(d0,d1,sel:IN BIT;
q:OUT BIT);
END GGG;
ARCHITECTURE connect OF GGG IS
SIGNAL tmp:BIT;
BEGIN
cale:PROCESS(d0,d1,sel)
VARIABLE
www.eeworm.com/read/149929/12330633
vhd clkgen.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY clkgen IS
PORT (
clk : IN STD_LOGIC;
newclk : OUT STD_LOGIC
);
END clkgen;
ARCHITECTURE A OF clkgen IS
SI