counter.vhd

来自「本频率计具有测周、测频、测量占空比等基本功能」· VHDL 代码 · 共 78 行

library ieee;
use ieee.std_logic_1164.all;
 
entity Counter is
port
(clk1,clk2:in std_logic;     --clk1为待计数信号，clk2为计数时钟
 result1,result2,result3:out integer range 0 to 9;
 over,low:out std_logic
);
end;

architecture a of Counter is
signal en,en1:std_logic;
signal num1,num2,num3:integer range 0 to 9;
signal overmode:std_logic;

begin
  process(clk1)
  begin
    if rising_edge(clk1) then
      en<=not en;
    end if;
  end process;

  process(clk2)
  begin
    if rising_edge(clk2) then
      if en='1' then
        if en1='1' then
          en1<='0';
          if overmode='1' then
            low<='0';
            over<='1';
            overmode<='0';
          elsif num3=0 then
            low<='1';
            over<='0';
           else
            low<='0';
            over<='0';
            result1<=num1;
            result2<=num2;
            result3<=num3;
           end if;

           num1<=0;
           num2<=0;
           num3<=0;
         end if;
        else
          en1<='1';
          low<='0';
          over<='0';
          if num1=9 then
           if num2=9 then
            if num3=9 then
             overmode<='1';
            else 
             overmode<='0';
             num3<=num3+1;
             num2<=0;
             num1<=0;
            end if;
           else
             overmode<='0';
             num2<=num2+1;
             num1<=0;
           end if;
          else
             overmode<='0';
             num1<=num1+1;
          end if;
        end if;
      end if;
     end process;
   end a;