代码搜索：Process
找到约 10,000 项符合「Process」的源代码
代码结果 10,000
www.eeworm.com/read/490627/6450105
c semaph.c
/*
* Provide an simpler and easier to understand interface to the System V
* semaphore system calls. There are 7 routines available to the user:
*
* id = sem_create(key, initval); # create with i
www.eeworm.com/read/490377/6455666
plg 1.plg
礦ision3 Build Log
Project:
C:\Documents and Settings\Administrator\桌面\新建文件夹 (4)\发射\1.uv2
Project File Date: 02/24/2009
Output:
Build target 'T
www.eeworm.com/read/490438/6456422
vhd jianzhong.vhd
entity jianzhong is
port(clk,clr,s0,s1,s2,s3,s4,s5,s6:in bit;
ds:buffer bit_vector (3 downto 0);
y:buffer bit_vector (7 downto 0));
end jianzhong;
architecture zhong of jianzhong
www.eeworm.com/read/489800/6461514
vhd jkff.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY jk IS
PORT(clk,clr,pset,j,k: IN STD_LOGIC;
q,qb : buffer STD_LOGIC);
END jk;
ARCHITECTURE jk1 OF jk IS
BEGIN
process
www.eeworm.com/read/489745/6469227
txt 123.txt
#include
#include
#include
#include
#include
int P_NUM;
#define P_TIME 50
enum state
{
ready,
run,
block,
finish
};
str
www.eeworm.com/read/489753/6469261
txt dengjingdupinglvji.txt
VHDL语言设计如下所示:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity a is
port(clk:in std_logic;
tclk:in std_logic;
www.eeworm.com/read/488958/6480310
plg 24cxx.plg
礦ision2 Build Log
Project:
C:\prog\实验板\例程源码\24CXX读写\C\24CXX.uv2
Project File Date: 09/13/2007
Output:
Build target 'Target 1'
assembling STAR
www.eeworm.com/read/488056/6495529
cs processexecute.cs
using System;
using System.Collections.Generic;
using System.Text;
using System.Runtime.InteropServices;
using System.Threading;
namespace iPhoneUI
{
class ProcessExecute
{
www.eeworm.com/read/488200/6497989
h proc.h
#ifndef _PROC_H
#define _PROC_H
#include
#ifndef _MBUF_H
#include "mbuf.h"
#endif
#ifndef _TIMER_H
#include "timer.h"
#endif
#define SIGQSIZE 200 /* Entries in ksignal queu
www.eeworm.com/read/487908/6501825
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l