📄 dengjingdupinglvji.txt
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VHDL语言设计如下所示:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity a is
port(clk:in std_logic;
tclk:in std_logic;
start:in std_logic;
alarm0,alarm1:out std_logic;
dian:out std_logic_vector(3 downto 0);
data1:out integer range 0 to 9999);
end a;
architecture behav of a is
signal q:integer range 0 to 9999;
signal q1:integer range 0 to 10000;
signal q2:integer range 0 to 20000;
signal en,en1:std_logic;
signal qq,qqq:integer range 0 to 200000000;
signal data0:integer range 0 to 9999;
begin
process(clk)
begin
if clk'event and clk='1' then
if start='1' then q<=0;en<='0';
elsif q=9999 then q<=9999;en<='0';
else q<=q+1;en<='1';
end if;
end if;
end process;
process(tclk)
begin
if tclk'event and tclk='1' then
if start='1' then q1<=0;en1<='0';
elsif en='1' then q1<=q1+1;en1<='1';
else en1<='0';
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if start='1' then q2<=0;
elsif en1='1' then
if q2=20000 then q2<=20000;
else q2<=q2+1;
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if start='1' then data0<=0;dian<="0000";alarm0<='0';alarm1<='0';qqq<=0;qq<=00;
elsif en1='0' then
if q1>=1000 then qq<=q1*10000;
if qqq<qq then qqq<=qqq+q2;data0<=data0+1;dian<="0000";
elsif data0>=10000 then alarm0<='1';
else data1<=data0;
end if;
elsif q1>=100 then qq<=q1*100000;
if qqq<qq then qqq<=qqq+q2;data0<=data0+1;
elsif data0>=10000 then data1<=1000;dian<="0000";
else data1<=data0;dian<="0010";
end if;
elsif q1>=10 then qq<=q1*1000000;
if qqq<qq then qqq<=qqq+q2;data0<=data0+1;
elsif data0>=10000 then data1<=1000;dian<="0010";
else data1<=data0;dian<="0100";
end if;
elsif q1>=1 then qq<=q1*10000000;
if qqq<qq then qqq<=qqq+q2;data0<=data0+1;
elsif data0>=10000 then data1<=1000;dian<="0100";
else data1<=data0;dian<="1000";
end if;
end if;
elsif q2>19999 then alarm1<='1';
else alarm1<='0';
end if;
end if;
end process;
end behav;
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