代码搜索：Process
找到约 10,000 项符合「Process」的源代码
代码结果 10,000
www.eeworm.com/read/460614/7245571
qmsg top.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/460489/7248831
cpp stdafx.cpp
// stdafx.cpp : source file that includes just the standard includes
// Process.pch will be the pre-compiled header
// stdafx.obj will contain the pre-compiled type information
#include "stdafx.h
www.eeworm.com/read/460356/7252850
plg current.plg
礦ision2 Build Log
Project:
E:\Program\第20章\Current\Current.uv2
Project File Date: 08/22/2007
Output:
Build target 'Target 1'
assembling START
www.eeworm.com/read/460345/7253102
plg voicesysy.plg
礦ision2 Build Log
Project:
E:\Program\第19章\VoiceSYS\VoiceSYSY.uv2
Project File Date: 08/21/2007
Output:
Build target 'Target 1'
assembling ST
www.eeworm.com/read/460213/7255467
vhd counter24.vhd
--counter24
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter24 is
port(clk:in std_logic;
bcd1:out std_logic_vector
www.eeworm.com/read/460213/7255489
vhd counter24.vhd
--counter24
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter24 is
port(clk:in std_logic;
bcd1:out std_logic_vector
www.eeworm.com/read/460213/7255517
vhd fredivn.vhd
--evev frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn is
GENERIC (N:integer:=8);
port (clk:in std
www.eeworm.com/read/460213/7255521
vhd fredivn.vhd
--evev frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn is
GENERIC (N:integer:=8);
port (clk:in std
www.eeworm.com/read/460213/7255522
vhd fredivn1.vhd
--odd frequency division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fredivn1 is
GENERIC (N:integer:=15);
port (clk:in
www.eeworm.com/read/460213/7255525
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log