top.map.qmsg

msp430驱动340*240程序 包括显示图片 文字 以及一些改变字体颜色功能等

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 09 13:12:19 2008 " "Info: Processing started: Tue Dec 09 13:12:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dds.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dds-one " "Info: Found design unit 1: dds-one" {  } { { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "McuToFpga.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file McuToFpga.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 McuToFpga-behav " "Info: Found design unit 1: McuToFpga-behav" {  } { { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 McuToFpga " "Info: Found entity 1: McuToFpga" {  } { { "McuToFpga.vhd" "" { Text "D:/xinhaoyuan/FPGA/McuToFpga.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sinrom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sinrom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sinrom-one " "Info: Found design unit 1: sinrom-one" {  } { { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sinrom " "Info: Found entity 1: sinrom" {  } { { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 top-behav " "Info: Found design unit 1: top-behav" {  } { { "top.vhd" "" { Text "D:/xinhaoyuan/FPGA/top.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.vhd" "" { Text "D:/xinhaoyuan/FPGA/top.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pll.vhd 2 1 " "Warning: Using design file pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll-SYN " "Info: Found design unit 1: pll-SYN" {  } { { "pll.vhd" "" { Text "D:/xinhaoyuan/FPGA/pll.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.vhd" "" { Text "D:/xinhaoyuan/FPGA/pll.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll pll:inst1 " "Info: Elaborating entity \"pll\" for hierarchy \"pll:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 336 200 440 496 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll:inst1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"pll:inst1\|altpll:altpll_component\"" {  } { { "pll.vhd" "altpll_component" { Text "D:/xinhaoyuan/FPGA/pll.vhd" 127 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pll:inst1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"pll:inst1\|altpll:altpll_component\"" {  } { { "pll.vhd" "" { Text "D:/xinhaoyuan/FPGA/pll.vhd" 127 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "top top:inst " "Info: Elaborating entity \"top\" for hierarchy \"top:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 192 624 808 320 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "McuToFpga top:inst\|McuToFpga:u1 " "Info: Elaborating entity \"McuToFpga\" for hierarchy \"top:inst\|McuToFpga:u1\"" {  } { { "top.vhd" "u1" { Text "D:/xinhaoyuan/FPGA/top.vhd" 49 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dds top:inst\|dds:u2 " "Info: Elaborating entity \"dds\" for hierarchy \"top:inst\|dds:u2\"" {  } { { "top.vhd" "u2" { Text "D:/xinhaoyuan/FPGA/top.vhd" 58 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "acc dds.vhd(24) " "Warning (10492): VHDL Process Statement warning at dds.vhd(24): signal \"acc\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "address dds.vhd(25) " "Warning (10492): VHDL Process Statement warning at dds.vhd(25): signal \"address\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "dds.vhd" "" { Text "D:/xinhaoyuan/FPGA/dds.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sinrom top:inst\|sinrom:u3 " "Info: Elaborating entity \"sinrom\" for hierarchy \"top:inst\|sinrom:u3\"" {  } { { "top.vhd" "u3" { Text "D:/xinhaoyuan/FPGA/top.vhd" 66 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DAOUT sinrom.vhd(532) " "Warning (10492): VHDL Process Statement warning at sinrom.vhd(532): signal \"DAOUT\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sinrom.vhd" "" { Text "D:/xinhaoyuan/FPGA/sinrom.vhd" 532 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pll:inst1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"pll:inst1\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "pll.vhd" "" { Text "D:/xinhaoyuan/FPGA/pll.vhd" 127 -1 0 } } { "Block1.bdf" "" { Schematic "D:/xinhaoyuan/FPGA/Block1.bdf" { { 336 200 440 496 "inst1" "" } } } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "327 " "Info: Implemented 327 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "313 " "Info: Implemented 313 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 09 13:12:29 2008 " "Info: Processing ended: Tue Dec 09 13:12:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}