代码搜索：Process

找到约 10,000 项符合「Process」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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m51 14-1.m51

BL51 BANKED LINKER/LOCATER V4.20 09/02/2001 15:12:55 PAGE 1 BL51 BANKED LINKER/LOCATER V4.20, INVOKED BY: C:\KEIL\C51\BIN\BL51.EXE 14-1.o
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plg 14-1.plg

Build target 'Target 1' compiling 14-1.c... linking... *** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS SEGMENT: ?PR?READDATA?14_1 *** WARNING L15: MULTIPLE CALL TO SEGMENT SEGM
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plg 10.1.plg

Build target 'Target 1' compiling 10.1.c... linking... *** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS SEGMENT: ?PR?_DAQ?10_1 *** WARNING L10: CANNOT DETERMINE ROOT SEGMENT "10.1"
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vhd cnt6.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY cnt6 IS PORT(reset,en,clk:IN STD_ULOGIC; carry1:OUT STD_ULOGIC; q:OUT STD_ULOGIC_VECTOR( 2 DOWNTO 0)); E
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vhd cnt4.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY cnt4 IS PORT(reset,en,clk:IN STD_ULOGIC; carry1:OUT STD_ULOGIC; q:OUT STD_ULOGIC_VECTOR( 1 DOWNTO 0)); E
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txt contr.txt

--控制模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity contr is port (cp100:in std_logic; --100Hz时钟 reset:in std_logic;
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txt shan.txt

--10000分频电路 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity shan is --10000分频电路 port( clk: in std_logic;
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m e271.m

%----------------------------------------------------------------------- % Example 2.7.1: Chemical Absorption Process %----------------------------------------------------------------------- % I
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vhd latchinf.vhd

-- MAX+plus II VHDL Example -- Latch Inference -- Copyright (c) 1994 Altera Corporation Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY latchinf IS PORT ( enable, data : IN BIT;
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vhd uart_ls.vhd

---------------------------------------------------------------- -- -- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rights reserved. -- -------------------------------------------------------
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