shan.txt

来自「用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环」· 文本 代码 · 共 34 行

--10000分频电路

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;


entity shan is                                --10000分频电路
   port(
       clk:  in  std_logic;
       cp100:out std_logic);
end shan;

architecture fenpin of shan is
   signal tout  :integer range 0 to 10000;
   signal cpfen :std_logic;
begin
   process(clk)
   begin
     if (clk'event and clk='0') then
        if tout=9999 then
           tout<=0;
        else 
           tout<=tout+1;
        end if;
        if tout<=4999 then
           cp100<='0';
        else
           cp100<='1';
        end if;
     end if;
   end process;
end fenpin;