代码搜索：Pattern recognition
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www.eeworm.com/read/129814/14223885
t brkcont.t
name: break-1
description:
See if break breaks out of loops
stdin:
for i in a b c; do echo $i; break; echo bad-$i; done
echo end-1
for i in a b c; do echo $i; break 1; echo bad-$i; done
echo end-
www.eeworm.com/read/226770/14452927
c matchtest.c
#include "match.h"
#include "buffer.h"
#include "str.h"
int main(int argc,char **argv)
{
const char *pattern = "";
const char *buf = "";
if (argv[1]) {
pattern = argv[1];
if (argv[2])
www.eeworm.com/read/125782/14462633
c m_driver.c
/****************************************************************************
* Copyright (c) 1998,2000 Free Software Foundation, Inc. *
*
www.eeworm.com/read/218331/14926343
c getsdir.c
/*
* getsdir.c
*
* Get and return a sorted directory listing
*
* Copyright (c) 1998 by James S. Seymour (jseymour@jimsun.LinxNet.com)
*
* This code is free software; you can redistribute it and
www.eeworm.com/read/212331/15159628
h leds.h
/****************************************************************************
Copyright (C) Cambridge Silicon Radio Ltd. 2004-2006
This file was autogenerated by ledparse and
provides si
www.eeworm.com/read/212320/15159895
cpp combodlg.cpp
// ComboDlg.cpp : implementation file
//
#include "stdafx.h"
#include "Ex_CommCtrls.h"
#include "ComboDlg.h"
#ifdef _DEBUG
#define new DEBUG_NEW
#undef THIS_FILE
static char THIS_FILE[] =
www.eeworm.com/read/211682/15175583
txt readme.txt
XAPP577 version 1.2 reference design files:
Verilog Directory:
hd_sep_demo.v: Top-level module for the separate Rx & Tx demo
hd_sep_demo.ucf: Contraints file for the sep
www.eeworm.com/read/205842/15305673
vec fir_compiler.vec
% units default to ns %
START 0 ;
STOP 1495 ;
INTERVAL 5 ;
INPUTS clk ;
PATTERN
0 1 ; % relative vector values %
% CLOCK ticks every INTERVAL %
INPUTS rst;
PATTERN
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vec fir32a.vec
% units default to ns %
START 0 ;
STOP 1495 ;
INTERVAL 5 ;
INPUTS clk ;
PATTERN
0 1 ; % relative vector values %
% CLOCK ticks every INTERVAL %
INPUTS rst;
PATTERN