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new_pwm.flow.rpt

Flow report for new_pwm Thu Nov 15 10:18:49 2007 Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; ---------------------

new_pwm.sim.rpt

Simulator report for new_pwm Thu Nov 15 11:34:41 2007 Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; -------------------

new_pwm.vhd.bak

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity new_pwm is port(clk:in std_logic; wrData:in std_logic_vector(15 downto 0); PwmOut:out std_logic); end entity

new_pwm.map.eqn

-- Copyright (C) 1991-2007 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o

new_pwm.map.summary

Analysis & Synthesis Status : Successful - Thu Nov 15 10:18:49 2007 Quartus II Version : 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition Revision Name : new_pwm Top-level Entity Name : new_pwm Family

pwm16bits.v

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:32:05 12/18/2008 // Design Name: // Mo