pwm16bits.v

SPI总线Master的verilog代码

	
	`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:32:05 12/18/2008 
// Design Name: 
// Module Name:    pwm 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
	module pwm16bits(clk, data, pwm_out, clr_n);
	
	input  clk;
	input [15:0] data;
	input clr_n;
	output pwm_out;
	
	reg [15:0] period = 16'b1111111111111111;
	reg [15:0] pulse_width;
	reg [15:0] counter;
	reg [15:0] filter;
	reg [15:0] distance;
	reg off ;
	reg new_data = 1;
	reg under_filter = 0;
	
//////////////////////	  this is a filter
        always @(posedge new_data)
		   	begin
				   
					filter =  pulse_width;
					distance = (data < pulse_width)?(filter-data):(data-filter);
					if(distance <= ((data<pulse_width)?(data/2):(pulse_width/2))) begin filter = data;under_filter =0;end
						else begin 
							if(distance > (data>filter?data:filter)/2)
							   filter  = (data < pulse_width)?(filter>>1):((filter<<1));
							else filter  = (data < pulse_width)?(filter - distance/2):((filter + distance/2));
						end
						
				end
				
				
//////////////////////	  this is 		
		
	always @(posedge clk or negedge clr_n)
		begin
			if (clr_n==0)
				begin
					pulse_width <= 16'b0000000000000000;
					filter <= 16'b0000000000000000;
				end
			else	
				begin
					if (new_data && !under_filter)  
						begin 
							pulse_width <= data[15:0];
							filter <= pulse_width;
							new_data = 0;
							under_filter =1; 
						end
					else if(new_data && under_filter) 
						begin pulse_width <= filter; 
						new_data = 0; 
						end
					else pulse_width <= pulse_width;
				end
	  end

////////////////////////////////////////////	  counter 				
   
	always @(posedge clk or negedge clr_n)
		begin
		  if (clr_n==0) counter <= 0;
		  else if (counter>=period-1) begin counter <= 0;new_data = 1; end
		  else counter <= counter+1;
		end
		
		
////////////////////////////////////////////	 output   		
	always @(posedge clk or negedge clr_n)
	  begin
		 if (clr_n == 0) off <= 0;
		 else if (counter >= pulse_width) off <= 1;
		 else if (counter==0) off <= 0;
		 else off <= 0;
	 end
	assign pwm_out=!off;	
	endmodule