代码搜索结果

#define VFD_DGT0 0 // The following define is depend on PCB layout #define VFD_DGT1 2 // address 2,3 #define VFD_DGT2 4 // address 4,5 #define VFD_DGT3 6 // address 6,7

PCB网城共享资源帮助文档

G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 Layout Name: E:/at91/9200_ext/pcb/9200_ext_20070706-gerber.brd* G04 Film Name: TOP* G04 File Format: Gerber RS27

This is the ChipWeb

Protel Design System Design Rule Check PCB File : \Protel DXP 2004\Design\chapter15\计数器电路设计.PCBDOC Date : 2005-7-12 Time : 0:12:35 Processing Rule : Hole Size Constraint (Min=0.0254mm) (

coolbor工作室——PCB设计（Protel） .ie{scrollbar-arrow-color:ccff66;scrollbar-face-colo

Protel Design System Design Rule Check PCB File : \Protel DXP 2004\Design\chapter13\U盘电路设计.PCBDOC Date : 2005-5-22 Time : 16:21:22 Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3

Board Information Report Filename : F:\M128\128数控板\MEGA128_DEV1.1.pcb Date : 2007-7-27 Time : 17:16:51 Time Elapsed : 00:00:00 Plated Hole Size, Pads, Vias 0mm, 534, 0

DRC Rules Export File for PCB: F:\M128\128数控板\MEGA128_DEV1.1.pcbdoc RuleKind=Width|RuleName=Width_5|Scope=Board|Minimum=25.00 RuleKind=Width|RuleName=Width_4|Scope=Board|Minimum=25.00 RuleKind=Widt

Protel Design System Design Rule Check PCB File : \Protel DXP 2004\Design\chapter13\U盘电路设计.PCBDOC Date : 2005-5-22 Time : 16:21:22 Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3