计数器电路设计.drc

来自「此电路为计时器电路设计原理图」· DRC 代码 · 共 30 行

Protel Design System Design Rule Check
PCB File : \Protel DXP 2004\Design\chapter15\计数器电路设计.PCBDOC
Date     : 2005-7-12
Time     : 0:12:35

Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3mm) (Preferred=0.2mm) (All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=0.25mm) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.3mm) (Max=0.5mm) (Preferred=0.5mm) (InNet('VCC')  Or InNet('GND'))
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:12