代码搜索：Numeric
找到约 7,754 项符合「Numeric」的源代码
代码结果 7,754
www.eeworm.com/read/367675/2836538
txt 435.txt
发信人: eastcamel (Happy Digger!), 信区: DataMining
标 题: Re: 谁有“ChiMerge:discretization of numeric attribut
发信站: 南京大学小百合站 (Wed Jul 24 16:56:32 2002), 站内信件
google it
【 在 hmx (star) 的大作中提到: 】
:
www.eeworm.com/read/471796/6881974
vhd list_ch04_15_disp_hex.vhd
-- Listing 4.15
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity disp_hex_mux is
port(
clk, reset: in std_logic;
hex3, hex2, hex1, hex0: in std_logic_v
www.eeworm.com/read/102471/15780245
vhd sdrm_t.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
library UNISIM;
--use UNISIM.vcomponents.all;
entity sdrm_t is
port ( sd_add_o: out unsigned(10 downto 0);
sd_ras_o: out std_log
www.eeworm.com/read/387009/8712267
h elliptint.h
Doub rc(const Doub x, const Doub y) {
static const Doub ERRTOL=0.0012, THIRD=1.0/3.0, C1=0.3, C2=1.0/7.0,
C3=0.375, C4=9.0/22.0;
static const Doub TINY=5.0*numeric_limits::min(),
BIG=0
www.eeworm.com/read/428887/8831496
jp
# 06sep07abu
# (c) Software Lab. Alexander Burger
"Language" "言語"
# lib/db.l
"Boolean input expected" "Booleanタイプが必要"
"Numeric input expected" "数値入力が必要"
"Symbolic type expected" "Symbolicタイプが必要"
"St
www.eeworm.com/read/428603/8856512
vhd scandispled.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
entity displed is
Port ( ps2clk,ps2data,clk50: in STD_LOGIC;
www.eeworm.com/read/371614/9546154
vhd lab5stopwatch.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab5stopwatch is
port(
up, clk: in std_logic;
go, clr: in std_logic;
d3, d2, d1, d0:out std_lo
www.eeworm.com/read/371614/9546351
bak lab5stopwatch.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab5stopwatch is
port(
up, clk: in std_logic;
go, clr: in std_logic;
d3, d2, d1, d0:out std_lo
www.eeworm.com/read/332405/12759624
vhd brst_cntr.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
entity brst_cntr is
port ( brst_end: out std_logic;
brst_end_m1: out std_logic;
Reset: in std_logic;
Clk: in std_logic;
ld_brs
www.eeworm.com/read/332405/12759767
vhd ref_cntr.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_STD.all;
entity ref_cntr is
port ( auto_ref: out std_logic;
p_auto_ref: out std_logic;
Reset: in std_logic;
Clk: in std_logic;
clr_ref: