代码搜索：ModelSim-Altera
找到约 12 项符合「ModelSim-Altera」的源代码
代码结果 12
www.eeworm.com/read/439524/7706943
doc modelsim-altera 6.1g破解.doc
www.eeworm.com/read/349736/10801543
pdf 如何破解modelsim-altera 6.1g.pdf
www.eeworm.com/read/459121/7282362
sft kkd.sft
set tool_name "ModelSim-Altera (Verilog)"
set corner_file_list {
{{"Slow Model"} {kkd.vo kkd_v.sdo}}
}
www.eeworm.com/read/375321/9364167
rpt top_nativelink_simulation.rpt
Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
========= EDA Simulation Settings =====================
Sim Mode
www.eeworm.com/read/349736/10801553
pdf 如何解決在quartus ii无法使用modelsim-altera模拟的問題.pdf
www.eeworm.com/read/17749/755430
sft kkd.sft
set tool_name "ModelSim-Altera (Verilog)"
set corner_file_list {
{{"Slow Model"} {kkd.vo kkd_v.sdo}}
}
www.eeworm.com/read/450753/7477027
v divn.v
/*
(C) OOMusou 2008 http://oomusou.cnblogs.com
Filename : divn.v
Compiler : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
Description : Demo how to write frequency divider by n
Release :
www.eeworm.com/read/450753/7477023
v counter60.v
/*
(C) OOMusou 2008 http://oomusou.cnblogs.com
Filename : counter60.v
Compiler : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
Description : Demo how to write 60 counter
Release : 07/27/
www.eeworm.com/read/450753/7477024
v digi_clock.v
/*
(C) OOMusou 2008 http://oomusou.cnblogs.com
Filename : digi_clock.v
Compiler : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
Description : Demo how to write digital clock top module
Relea
www.eeworm.com/read/450753/7477025
v counter24.v
/*
(C) OOMusou 2008 http://oomusou.cnblogs.com
Filename : counter24.v
Compiler : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
Description : Demo how to write 24 counter
Release : 07/27/