代码搜索：Maxplus
找到约 394 项符合「Maxplus」的源代码
代码结果 394
www.eeworm.com/read/146918/12603794
rpt my_add8.rpt
Project Information f:\maxplus_study\maxshiyan\add8\my_add8.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/27/2004 14:37:29
Copyright (C) 1988-2002 Al
www.eeworm.com/read/459533/7274140
vhd debouncing.vhd
--DEBOUNCING.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY ALTERA;
USE ALTERA.MAXPLUS2.ALL;
ENTITY DEBOUNCING IS
PORT(
D_IN, CLK: IN STD_LOGIC;
--DD1, DD0, QQ1, QQ0 : OUT
www.eeworm.com/read/442917/7642362
vhd elec_lock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library altera;
use altera.maxplus2.all;
entity elec_lock is
port(
clk_4M:in std_
www.eeworm.com/read/435453/7792209
txt erfenpin.txt
二分频
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.maxplus2.all;
entity freq2 is
port(clkin:in std_logic;
clkout:out std_logic);
end entity;
architecture rt1 of
www.eeworm.com/read/472423/6866963
rpt reg32b.rpt
Project Information c:\maxplus2\1502d\test11\reg32b.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/17/2002 13:50:53
Copyright (C) 1988-2000 Alt
www.eeworm.com/read/146918/12604246
rpt my_74ls138.rpt
Project Information f:\maxplus_study\tt\my_74ls138\my_74ls138.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/15/2004 16:06:33
Copyright (C) 1988-2002 Al
www.eeworm.com/read/307578/13720257
vhd debouncing.vhd
--DEBOUNCING.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY ALTERA;
USE ALTERA.MAXPLUS2.ALL;
ENTITY DEBOUNCING IS
PORT(D_IN, CLK: IN STD_LOGIC;
DD1, DD0, QQ1, QQ0 : OUT STD_L
www.eeworm.com/read/402992/11525393
vhd debouncing.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY debouncing IS
PORT
(
d_in, clk : IN STD_LOGIC;
dd1, dd0, qq1, qq0 : OUT STD_LOGIC ;
d_ou
www.eeworm.com/read/255899/12047468
vhd shiftreg_4.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY shiftreg IS
PORT(Di,clk : IN STD_LOGIC;
Q3,Q2,Q1,Q0 : OUT STD_LOGIC);
END shiftreg;
ARCHITECTUR
www.eeworm.com/read/255899/12047496
vhd shiftreg_5.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY shiftreg IS
PORT(Di,clk : IN STD_LOGIC;
Q3,Q2,Q1,Q0 : OUT STD_LOGIC);
END shiftreg;
ARCHITE