代码搜索：Maxplus
找到约 394 项符合「Maxplus」的源代码
代码结果 394
www.eeworm.com/read/313201/13592324
vhd lcs.vhd
MaxPlus 10p2 VHDL results: Device = EPF10K70RC240-4
Chip/ Input Output Bidir Memory Memory LCs
POF Pins Pins Pins Bits % Utilized LCs % Utilized
add_1p 31 1
www.eeworm.com/read/115176/13867613
rpt translate_1.rpt
Project Information d:\maxplus2\0110200330\translation\translate_1.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/28/2004 15:48:21
Copyright (C) 1988-2002 Al
www.eeworm.com/read/115176/13867622
rpt translate_2.rpt
Project Information d:\maxplus2\0110200330\translation\translate_2.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/28/2004 15:50:23
Copyright (C) 1988-2002 Al
www.eeworm.com/read/404531/11483664
rpt traffic.rpt
Project Information c:\maxplus2\files\max\traffic\traffic.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 11/18/2002 14:37:52
Copyright (C) 1988-2000 Alt
www.eeworm.com/read/402992/11525402
vhd keyboard1.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY KEYBOARD1 IS
PORT (
clk
www.eeworm.com/read/260654/11712513
rpt 7to1.rpt
Project Information c:\maxplus2\multi\cpu\7to1.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 10/17/2006 11:47:51
Copyright (C) 1988-2001 Al
www.eeworm.com/read/260654/11712680
rpt yunsuan11.rpt
Project Information c:\maxplus2\multi\cpu\yunsuan11.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/18/2006 18:05:31
Copyright (C) 1988-2002 Al
www.eeworm.com/read/260654/11713125
rpt kongceshi2.rpt
Project Information c:\maxplus2\multi\cpu\kongceshi2.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/18/2006 09:45:34
Copyright (C) 1988-2002 Al
www.eeworm.com/read/155822/11844987
vhd p2s_altera.vhd
LIBRARY altera;
USE altera.maxplus2.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity p2s_altera is
port(
clk,
clkih,
stld,
ser: in std_logic;
d :in std_logic_vector(0 to
www.eeworm.com/read/255899/12047466
vhd shiftreg_8.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY shiftreg IS
PORT(Di,clk : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END shiftreg;
AR