代码搜索：Maxplus

找到约 394 项符合「Maxplus」的源代码

代码结果 394
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/140872/13055428

rpt sysclock.rpt

Project Information e:\mydesign\altera\maxplus\lisha\sysclock.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 05/07/2005 17:39:22 Copyright (C) 1988-2002 Al
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www.eeworm.com/read/140872/13055859

rpt bfenpin.rpt

Project Information e:\mydesign\altera\maxplus\lisha\bfenpin.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 05/07/2005 17:29:25 Copyright (C) 1988-2002 Al
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www.eeworm.com/read/115176/13867695

rpt fourcon.rpt

Project Information d:\maxplus2\0110200330\fourcon.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 11/28/2004 14:37:24 Copyright (C) 1988-2002 Al
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www.eeworm.com/read/489800/6461478

rpt scan_led.rpt

Project Information d:\vhdlexperiments\maxplus\1\scan_led.rpt MAX+plus II Compiler Report File Version 10.0 9/14/2000 Compiled: 05/04/2009 17:54:07 Copyright (C) 1988-2000 Alt
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www.eeworm.com/read/402992/11525354

vhd lock.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY lock IS PORT ( CLK
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www.eeworm.com/read/255899/12047418

vhd shiftreg_7.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY shiftreg IS GENERIC(width : integer:= 4); PORT(Di,clk : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(
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www.eeworm.com/read/149999/12326007

rpt fredevider.rpt

Project Information f:\maxplus2\vhd\fredevider.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 11/18/2005 15:13:01 Copyright (C) 1988-2002 Al
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www.eeworm.com/read/149999/12326400

rpt statemachine.rpt

Project Information f:\maxplus2\vhd\statemachine.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 11/18/2005 15:02:54 Copyright (C) 1988-2002 Al
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www.eeworm.com/read/149929/12332937

vhd usea74.vhd

LIBRARY IEEE; LIBRARY ALTERA; USE ALTERA.MAXPLUS2.ALL; USE IEEE.STD_LOGIC_1164.ALL; ENTITY USEA74 IS PORT( OEN,G:IN STD_LOGIC; D:IN STD_LOGIC_VECTOR(8 DOWNTO 1);
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www.eeworm.com/read/128342/14304074

rpt caiyang.rpt

Project Information c:\maxplus2\muxfile\caiyang.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 03/27/2005 11:51:34 Copyright (C) 1988-2002 Al
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