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NET "data" LOC = "p140" ; NET "data" LOC = "p139" ; NET "data" LOC = "p141" ; NET "data" LOC = "p4" ; NET "data" LOC = "p5" ; NET "data" LOC = "p6" ; NET "data

# ISim flow : Creating project file mcu_stx.prj mcu.isim_stx_prj work # ISim : Check Syntax for Simulation *.auxlib isim isim_temp xilinxsim.ini mcu.isim_stx_sim # ISim flow : Creating proje

set -tmpdir __projnav set -xsthdpdir ./xst run -ifn mcu.prj -ifmt mixed -ofn mcu -ofmt NGC -p xc2s50-6-tq144 -top mcu -opt_mode Speed -opt_level 1 -iuc NO -lso mcu.lso -keep_hierarchy NO

Release 7.1.04i par H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. CINDY:: Sat Feb 25 18:50:58 2006 par -w -intstyle ise -ol std -t 1 mcu_map.ncd mcu.ncd mcu.pcf Constraints fil

cpldfit: version H.42 Xilinx Inc. Fitter Report Design Name: mcu Date: 2-21-2006, 6:22PM Device

PROGRAM=PAR STATE=ROUTED TIMESPECS_MET=OFF

Release 7.1.04i ngdbuild H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -intstyle ise -dd e:\temp\spartan2\veriloge\interface\mcu/_ngo -nt timestamp -uc mcu.u

//! ************************************************************************** // Written by: Map H.42 on Sat Feb 25 18:50:36 2006 //! ***************************************************************

# begin LFP file E:\temp\95144\mcu\mcu.lfp designfile mcu.v parttype xc95144xl-tq144-10 bus_delimiter 0; set_busdelim_onsave 0; IO_GROUP "data" IO_GROUP="mcu" ; IO_GROUP "ledout" IO_GROUP="mcu"