📄 mcu.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: mcu Date: 2-21-2006, 6:22PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
18 /144 ( 12%) 44 /720 ( 6%) 34 /432 ( 8%) 10 /144 ( 7%) 27 /117 ( 23%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 2/18 3/54 4/90 0/15
FB2 0/18 0/54 0/90 0/15
FB3 8/18 11/54 24/90 8/15
FB4 1/18 5/54 2/90 1/15
FB5 0/18 0/54 0/90 0/14
FB6 6/18 10/54 12/90 6/13
FB7 0/18 0/54 0/90 0/15
FB8 1/18 5/54 2/90 1/15
----- ----- ----- -----
18/144 34/432 44/720 16/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 11 11 | I/O : 27 109
Output : 8 8 | GCK/IO : 0 3
Bidirectional : 8 8 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 27 27
** Power Data **
There are 18 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:1007 - Removing unused input(s) 'nrst'. The input(s) are unused
after optimization. Please verify functionality via simulation.
************************* Summary of Mapped Logic ************************
** 16 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
ledout<5> 3 4 FB3_5 33 I/O O STD FAST RESET
ledout<4> 3 4 FB3_9 40 I/O O STD FAST RESET
ledout<7> 3 4 FB3_10 48 I/O O STD FAST RESET
ledout<3> 3 4 FB3_11 43 I/O O STD FAST RESET
ledout<2> 3 4 FB3_12 45 I/O O STD FAST RESET
ledout<1> 3 4 FB3_14 49 I/O O STD FAST RESET
ledout<6> 3 4 FB3_15 50 I/O O STD FAST RESET
ledout<0> 3 4 FB3_17 51 I/O O STD FAST RESET
data<6> 2 5 FB4_1 118 I/O I/O STD FAST
data<0> 2 5 FB6_2 106 I/O I/O STD FAST
data<2> 2 5 FB6_4 111 I/O I/O STD FAST
data<3> 2 5 FB6_8 113 I/O I/O STD FAST
data<5> 2 5 FB6_9 116 I/O I/O STD FAST
data<4> 2 5 FB6_10 115 I/O I/O STD FAST
data<7> 2 5 FB6_11 119 I/O I/O STD FAST
data<1> 2 5 FB8_16 107 I/O I/O STD FAST
** 2 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
la<1> 2 2 FB1_17 STD RESET
la<0> 2 2 FB1_18 STD RESET
** 11 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
dial<4> FB5_3 59 I/O I
dial<1> FB5_7 66 I/O I
dial<7> FB5_8 56 I/O I
dial<6> FB5_9 57 I/O I
dial<5> FB5_11 58 I/O I
dial<3> FB5_14 61 I/O I
dial<2> FB5_15 64 I/O I
dial<0> FB5_17 69 I/O I
mcu_wr FB8_13 103 I/O I
mcu_rd FB8_14 102 I/O I
mcu_ale FB8_17 105 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 3/51
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 23 I/O
(unused) 0 0 0 5 FB1_2 16 I/O
(unused) 0 0 0 5 FB1_3 17 I/O
(unused) 0 0 0 5 FB1_4 25 I/O
(unused) 0 0 0 5 FB1_5 19 I/O
(unused) 0 0 0 5 FB1_6 20 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 21 I/O
(unused) 0 0 0 5 FB1_9 22 I/O
(unused) 0 0 0 5 FB1_10 31 I/O
(unused) 0 0 0 5 FB1_11 24 I/O
(unused) 0 0 0 5 FB1_12 26 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 27 I/O
(unused) 0 0 0 5 FB1_15 28 I/O
(unused) 0 0 0 5 FB1_16 35 I/O
la<1> 2 0 0 3 FB1_17 30 GCK/I/O (b)
la<0> 2 0 0 3 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: data<0>.PIN 2: data<1>.PIN 3: mcu_ale
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
la<1> .XX..................................... 2
la<0> X.X..................................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 142 I/O
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 0 5 FB2_5 2 GTS/I/O
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 0 5 FB2_11 9 I/O
(unused) 0 0 0 5 FB2_12 10 I/O
(unused) 0 0 0 5 FB2_13 12 I/O
(unused) 0 0 0 5 FB2_14 11 I/O
(unused) 0 0 0 5 FB2_15 13 I/O
(unused) 0 0 0 5 FB2_16 14 I/O
(unused) 0 0 0 5 FB2_17 15 I/O
(unused) 0 0 0 5 FB2_18 (b)
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 11/43
Number of signals used by logic mapping into function block: 11
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 39 I/O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
(unused) 0 0 0 5 FB3_3 41 I/O
(unused) 0 0 0 5 FB3_4 44 I/O
ledout<5> 3 0 0 2 FB3_5 33 I/O O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 46 I/O
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