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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity HOUR is port(clk,en:in std_logic; h1,h0:out std_logic_vector(3 downto 0)); end HOUR; architecture hour_

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity SECOND is port(clk,clr:in std_logic; sec1,sec0:out std_logic_vector(3 downto 0); co:out std_logic);

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity MINUTE is port(clk,en:in std_logic; min1,min0:out std_logic_vector(3 downto 0); co:out std_logic); e

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity SELTIME is port( clk:in std_logic;------扫描时钟 secm1,secm0,sec1,

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity HOUR is port(clk,en:in std_logic;----输入时钟/高电平有效的使能信号 h1,h0:out std_logic_vector(3 downto 0));----时高位/低位 en

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity SECOND is port(clk,clr:in std_logic;----时钟/清零信号 sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity MINUTE is port(clk,en:in std_logic; min1,min0:out std_logic_vector(3 downto 0); co:out std_logic); e

library ieee; use ieee.std_logic_1164.all; entity write_reg is port( ale : in std_logic; ad_in : in std_logic_vector(7 downto 0); sa_h : in std_logic_vector(15 downto 8);

--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity i60bcd i

--regne.vhd n-bit register with enable library ieee ; use ieee.std_logic_1164.all ; entity regne is generic ( n : integer := 12 ) ; port ( r : in std_logic_vector(n-1 downto 0) ;--register