write_reg.vhd

rs422协议的通讯程序.做一些简单改动即可以移植到各种环境。

library ieee;

use ieee.std_logic_1164.all;

entity write_reg is port(
		ale						: in std_logic;
		ad_in					: in std_logic_vector(7 downto 0);
		sa_h					: in std_logic_vector(15 downto 8);
		iow						: in std_logic;
		ior						: in std_logic;
		rst						: in std_logic;
		sa_l					: out std_logic_vector(7 downto 0);
----------a3 out-------------------- 		
		conn_on					: out std_logic;
		open_door				: out std_logic;
		allow					: out std_logic;
		fight					: out std_logic;
		torpedo_on				: out std_logic;
-----------led out-------------------------		
		pesudo_LED				: out std_logic;
		run_led					: out std_logic;
		rio_led					: out std_logic;
		ad_led					: out std_logic;
		cpu_led					: out std_logic;
------------y7b out---------------------------
		tube					: out std_logic;
		naborne					: out std_logic;
		paborne					: out std_logic;
		gulock					: out std_logic;
		cmdr					: out std_logic;
		sddr					: out std_logic;
----送预置控制器的显示参数-------------------------		
		cm_err_code 			: out std_logic_vector(3 downto 0);--cm出错编码
		sd_err_code 			: out std_logic_vector(3 downto 0);--sd出错编码
--------回送方式标志位--------------
--0=正常数据回送，1=错误码回送
		tc 						: out std_logic;	
--------状态灯-----
		y7b_err_led				: out  std_logic;
		y7b_put_led				: out  std_logic;
		y7b_ready_led			: out  std_logic;
		-------使预置控制器的mode led闪动------------
		flash_mode_led			: out std_logic;--送到串行16位的第tx(7)位，到预置控制器
		rst_flash_mode_led		: in std_logic;--来自预置控制器串行16位的第rx(9)位
		flash_ready_led			: out std_logic;--tx(10)='1',使ready_led 闪烁。
		--使CM,SD的回送值从cm_err_code,sd_err_code取出
		XT						: OUT STD_LOGIC;
		XT_MODE					: OUT STD_lOGIC--用于CPU回送
			
);
end entity;

architecture write of write_reg is

component wri_reg8 is port(
		iow			: in std_logic;
		rst			: in std_logic;
		cs			: in std_logic;
		data_in		: in std_logic_vector(7 downto 0);
		data_out	: out std_logic_vector(7 downto 0)
		);
end component;

signal lock_adr : std_logic;
signal t_sa_l : std_logic_vector(7 downto 0);	
signal t_sa : 	std_logic_vector(15 downto 0);
-----------write led---------
signal reg_led : std_logic_vector(7 downto 0);
signal cs_reg_led : std_logic;
-----------write y7b------------------
signal cs_y7b_reg : std_logic;
signal y7b_reg : std_logic_vector(7 downto 0);
----------write a3---------------
signal cs_a3_reg : std_logic;
signal a3_reg : std_logic_vector(7 downto 0);
---------sd code--------------
signal t_err_sd_code    : std_logic_vector(7 downto 0);
-------cm code----------------
signal t_err_cm_code    : std_logic_vector(7 downto 0);
---------------------------
signal cs_lock_key : std_logic;


begin

sa_l <= t_sa_l;
t_sa <= sa_h & t_sa_l;

lock_adr <= not ale;
u_adr : wri_reg8 port map(
		iow			=> lock_adr,--: in std_logic;
		rst			=> rst,--: in std_logic;
		cs			=> '0',--: in std_logic;
		data_in		=> ad_in,--: in std_logic_vector(7 downto 0);
		data_out	=> t_sa_l--: out std_logic_vector(7 downto 0)
		);

--led drv reg
cs_reg_led <= '0' when t_sa=x"c006" else '1';
u_reg_led : wri_reg8 port map(
		iow			=> iow,--: in std_logic;
		rst			=> rst,--: in std_logic;
		cs			=> cs_reg_led,-- in std_logic;
		data_in		=> ad_in,--: in std_logic_vector(7 downto 0);
		data_out	=> reg_led--: out std_logic_vector(7 downto 0)
		);

pesudo_LED	<= not reg_led(0);
run_led		<= not reg_led(1);
rio_led		<= not reg_led(2);
ad_led		<= not reg_led(3);
cpu_led		<= not reg_led(4);

--------------write y7b-----------
cs_y7b_reg <= '0' when t_sa=x"c005" else '1';
u_y7b_reg : wri_reg8 port map(
		iow			=> iow,--: in std_logic;
		rst			=> rst,--: in std_logic;
		cs			=> cs_y7b_reg,-- in std_logic;
		data_in		=> ad_in,--: in std_logic_vector(7 downto 0);
		data_out	=> y7b_reg--: out std_logic_vector(7 downto 0)
		);

tube		<= y7b_reg(0);	
naborne		<= y7b_reg(1);
paborne		<= y7b_reg(2);	
gulock		<= y7b_reg(3);	
cmdr		<= y7b_reg(4);
sddr		<= y7b_reg(5);

---------------write a3 out----------
cs_a3_reg <= '0' when t_sa=x"c004" else '1';
u_a3_reg : wri_reg8 port map(
		iow			=> iow,--: in std_logic;
		rst			=> rst,--: in std_logic;
		cs			=> cs_a3_reg,-- in std_logic;
		data_in		=> ad_in,--: in std_logic_vector(7 downto 0);
		data_out	=> a3_reg--: out std_logic_vector(7 downto 0)
		);

conn_on			<= a3_reg(0);
open_door		<= a3_reg(1);
allow			<= a3_reg(2);
fight			<= a3_reg(3);
torpedo_on 		<= a3_reg(4);

----送预置控制器的显示参数-------------------------		
--------回送方式标志位--------------
--0=正常数据回送，1=错误码回送
tc <= t_err_cm_code(3);
cm_err_code <= t_err_cm_code(7 downto 4);

--------状态灯-----
y7b_err_led <= t_err_cm_code(0);
y7b_put_led	<= t_err_cm_code(1);			
y7b_ready_led	<= t_err_cm_code(2);		
sd_err_code <= t_err_sd_code(3 downto 0);
XT_MODE <= T_ERR_SD_CODE(7);	
		
-------------write err cm code-----------
process(rst,iow,t_sa,ad_in)
begin
	if rst='0' then
		t_err_cm_code <= x"18";
	else
		if rising_edge(iow) then
			if t_sa=x"c002"	then
				t_err_cm_code <= ad_in;
			end if;
		end if;
	end if;			
end process;
------------write sd_reg--------
process(rst,iow,t_sa,ad_in)
begin
	if rst='0' then
		t_err_sd_code <= x"04";
		
	else
		if rising_edge(iow) then
			if t_sa=x"c003" then
				t_err_sd_code <= ad_in;
			end if;
		end if;
	end if;			
end process;

-------使预置控制器的mode led闪动------------
process(rst,rst_flash_mode_led,iow,t_sa,ad_in)
begin
	if rst='0' or rst_flash_mode_led='1' then
		flash_mode_led <= '0';
	else
		if rising_edge(iow) then	
			if t_sa=x"c00c" then
				flash_mode_led <= ad_in(0);
			end if;
		end if;
	end if;			
end process;

-------使预置控制器的rx_code(10)='1',使准备灯，cm,sd参数闪动------------
process(rst,rst_flash_mode_led,iow,t_sa,ad_in)
begin
	if rst='0' then
		flash_ready_led <= '0';
	else
		if rising_edge(iow) then	
			if t_sa=x"c00D" then
				flash_ready_led <= ad_in(0);
			end if;
		end if;
	end if;			
end process;


--使CM,SD的回送值从cm_err_code,sd_err_code取出
process(rst,rst_flash_mode_led,iow,t_sa,ad_in)
begin
	if rst='0' then
		XT <= '0';
	else
		if rising_edge(iow) then	
			if t_sa=x"c00E" then
				XT <= ad_in(0);
			end if;
		end if;
	end if;			
end process;

end architecture ;