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找到约 10,000 项符合
Logic Analyzer 的代码
ipdr.vhd
--****************************************************************************************************
-- Instruction pipeline register, data in register for ARM7TDMI-S processor
-- Designed by Rus
armshiftertesttop.vhd
--****************************************************************************************************
-- Shifter tester top entity for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 07.12.20
resltbitmask.vhd
--****************************************************************************************************
-- This module cleares/sets bit 0 and clears 1 of ALU bus for ARM7TDMI-S processor
-- Designed
fenpinpwm20m_10k.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpinpwm20M_10k is
port(
clk:in std_logic; ------时钟信号20MhZ
fout:out std_logic); -----频率信号输
fenpinadc0809.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpinadc0809 is
port(
clk:in std_logic; ------时钟信号20MhZ
fout:out std_logic); -----频率信号输出500K
qiankui.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity qiankui is
port(input: in std_logic_vector(11 downto 0); --输入信号
cl
piso.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PiSo is
port(clk : in std_logic;
clr : in std_logic;
din : in std_logic_vector(7 downto 0);
clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz
putin.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PUTIN IS
PORT(CP0,CP1:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR
show.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHOW IS
PORT( SI:IN STD_LOGIC_VECTOR(4 DOWNTO 0);
SOU:OUT STD_LOGIC_VECTOR(4 downto 0));
end SHOW;
ARCHITECTURE PART1 OF SHOW IS