piso.vhd

8位并行输入的数转换成串行输出

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PiSo is
 port(clk : in std_logic;
      clr : in std_logic;
      din : in std_logic_vector(7 downto 0);
     dout : out std_logic);
end;

architecture one of PiSo is
   signal cnt : std_logic_vector(2 downto 0);
   signal q   : std_logic_vector(7 downto 0);
begin 
process(clk)
begin
  if clk'event and clk='1' then
       cnt<=cnt+1;
  end if;
end process;

process(clk,clr)
begin
  if clr='1' then q<="00000000";
  elsif clk'event and clk='1' then
      if cnt>"000" then 
         q(7 downto 1)<=q(6 downto 0);
      elsif cnt="000" then
        q<=din;
      end if;
  end if;
end process;
dout<=q(7);
end;