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Logic Analyzer 的代码
test.vhd
library ieee;
use ieee.std_logic_1164.all;
entity test is
port(dout:out std_logic_vector(7 downto 0));
end;
architecture one of test is
begin
dout
psk.vhd
library ieee;
use ieee.std_logic_1164.all;
entity psk is
port(code:in std_logic;
q:in std_logic_vector(1 downto 0);
p6b:out std_logic_vector(5 downto 0));
end;
architecture one of p
cnt3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt3 is
port(clk:in std_logic;
clk10k:out std_logic);
end;
architecture one of cnt3 is
signal q: std_logi
reg32bit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg32bit is
port(load:in std_logic;
din:in std_logic_vector(31 downto 0);
dout:out std_logic_vector(31 downto 0));
end reg32bit;
archit
mul16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul16 is
port (clk:in std_logic;
a,b:in std_logic_vector(15 downto 0);
q:ou
decoder_3_8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_3_8 is
port(a,b,c,e1,e2,e3:in std_logic;
y:out std_logic_vector(7
rom256x8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY work;
USE work.ram_constants.ALL;
ENT
decoder_4_16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_4_16 is
port(a1,b1,c1,d1,g2a1,g2b1:in std_logic;
y1,y2:out std_logi
control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
h264header.vhd
-------------------------------------------------------------------------
-- H264 convert bits to bytes - VHDL
--
-- Written by Andy Henson
-- Copyright (c) 2008 Zexia Access Ltd
-- All rights r