psk.vhd

来自「dds信号发生器」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
entity psk is
port(code:in std_logic;
      q:in std_logic_vector(1 downto 0);
      p6b:out std_logic_vector(5 downto 0));
end;
architecture one of psk is
begin
process(q)
begin
   if q="11" and code='1' then p6b<="100000";
    else p6b<="000000";
   end if;
end process;
end;